Using Performance Counters

In [1]:
!mkdir -p tmp

Using perf

A Linux tool for accessing performance counters.

See also the Wiki documentation for perf.

In [2]:
!perf list
  branch-instructions OR branches                    [Hardware event]
  branch-misses                                      [Hardware event]
  bus-cycles                                         [Hardware event]
  cache-misses                                       [Hardware event]
  cache-references                                   [Hardware event]
  cpu-cycles OR cycles                               [Hardware event]
  instructions                                       [Hardware event]
  ref-cycles                                         [Hardware event]
  alignment-faults                                   [Software event]
  bpf-output                                         [Software event]
  context-switches OR cs                             [Software event]
  cpu-clock                                          [Software event]
  cpu-migrations OR migrations                       [Software event]
  dummy                                              [Software event]
  emulation-faults                                   [Software event]
  major-faults                                       [Software event]
  minor-faults                                       [Software event]
  page-faults OR faults                              [Software event]
  task-clock                                         [Software event]
  L1-dcache-load-misses                              [Hardware cache event]
  L1-dcache-loads                                    [Hardware cache event]
  L1-dcache-stores                                   [Hardware cache event]
  L1-icache-load-misses                              [Hardware cache event]
  LLC-load-misses                                    [Hardware cache event]
  LLC-loads                                          [Hardware cache event]
  LLC-store-misses                                   [Hardware cache event]
  LLC-stores                                         [Hardware cache event]
  branch-load-misses                                 [Hardware cache event]
  branch-loads                                       [Hardware cache event]
  dTLB-load-misses                                   [Hardware cache event]
  dTLB-loads                                         [Hardware cache event]
  dTLB-store-misses                                  [Hardware cache event]
  dTLB-stores                                        [Hardware cache event]
  iTLB-load-misses                                   [Hardware cache event]
  iTLB-loads                                         [Hardware cache event]
  node-load-misses                                   [Hardware cache event]
  node-loads                                         [Hardware cache event]
  node-store-misses                                  [Hardware cache event]
  node-stores                                        [Hardware cache event]
  branch-instructions OR cpu/branch-instructions/    [Kernel PMU event]
  branch-misses OR cpu/branch-misses/                [Kernel PMU event]
  bus-cycles OR cpu/bus-cycles/                      [Kernel PMU event]
  cache-misses OR cpu/cache-misses/                  [Kernel PMU event]
  cache-references OR cpu/cache-references/          [Kernel PMU event]
  cpu-cycles OR cpu/cpu-cycles/                      [Kernel PMU event]
  cstate_core/c3-residency/                          [Kernel PMU event]
  cstate_core/c6-residency/                          [Kernel PMU event]
  cstate_core/c7-residency/                          [Kernel PMU event]
  cstate_pkg/c2-residency/                           [Kernel PMU event]
  cstate_pkg/c3-residency/                           [Kernel PMU event]
  cstate_pkg/c6-residency/                           [Kernel PMU event]
  cstate_pkg/c7-residency/                           [Kernel PMU event]
  cycles-ct OR cpu/cycles-ct/                        [Kernel PMU event]
  cycles-t OR cpu/cycles-t/                          [Kernel PMU event]
  el-abort OR cpu/el-abort/                          [Kernel PMU event]
  el-capacity OR cpu/el-capacity/                    [Kernel PMU event]
  el-commit OR cpu/el-commit/                        [Kernel PMU event]
  el-conflict OR cpu/el-conflict/                    [Kernel PMU event]
  el-start OR cpu/el-start/                          [Kernel PMU event]
  instructions OR cpu/instructions/                  [Kernel PMU event]
  intel_bts//                                        [Kernel PMU event]
  intel_cqm/llc_occupancy/                           [Kernel PMU event]
  intel_cqm/local_bytes/                             [Kernel PMU event]
  intel_cqm/total_bytes/                             [Kernel PMU event]
  intel_pt//                                         [Kernel PMU event]
  mem-loads OR cpu/mem-loads/                        [Kernel PMU event]
  mem-stores OR cpu/mem-stores/                      [Kernel PMU event]
  msr/aperf/                                         [Kernel PMU event]
  msr/mperf/                                         [Kernel PMU event]
  msr/smi/                                           [Kernel PMU event]
  msr/tsc/                                           [Kernel PMU event]
  power/energy-cores/                                [Kernel PMU event]
  power/energy-pkg/                                  [Kernel PMU event]
  power/energy-ram/                                  [Kernel PMU event]
  ref-cycles OR cpu/ref-cycles/                      [Kernel PMU event]
  topdown-fetch-bubbles OR cpu/topdown-fetch-bubbles/ [Kernel PMU event]
  topdown-recovery-bubbles OR cpu/topdown-recovery-bubbles/ [Kernel PMU event]
  topdown-slots-issued OR cpu/topdown-slots-issued/  [Kernel PMU event]
  topdown-slots-retired OR cpu/topdown-slots-retired/ [Kernel PMU event]
  topdown-total-slots OR cpu/topdown-total-slots/    [Kernel PMU event]
  tx-abort OR cpu/tx-abort/                          [Kernel PMU event]
  tx-capacity OR cpu/tx-capacity/                    [Kernel PMU event]
  tx-commit OR cpu/tx-commit/                        [Kernel PMU event]
  tx-conflict OR cpu/tx-conflict/                    [Kernel PMU event]
  tx-start OR cpu/tx-start/                          [Kernel PMU event]
  uncore_imc_0/cas_count_read/                       [Kernel PMU event]
  uncore_imc_0/cas_count_write/                      [Kernel PMU event]
  uncore_imc_0/clockticks/                           [Kernel PMU event]
  uncore_imc_1/cas_count_read/                       [Kernel PMU event]
  uncore_imc_1/cas_count_write/                      [Kernel PMU event]
  uncore_imc_1/clockticks/                           [Kernel PMU event]
  uncore_imc_4/cas_count_read/                       [Kernel PMU event]
  uncore_imc_4/cas_count_write/                      [Kernel PMU event]
  uncore_imc_4/clockticks/                           [Kernel PMU event]
  uncore_imc_5/cas_count_read/                       [Kernel PMU event]
  uncore_imc_5/cas_count_write/                      [Kernel PMU event]
  uncore_imc_5/clockticks/                           [Kernel PMU event]

cache:
  l1d.replacement                                   
       [L1D data line replacements]
  l1d_pend_miss.fb_full                             
       [Cycles a demand request was blocked due to Fill Buffers inavailability]
  l1d_pend_miss.pending                             
       [L1D miss oustandings duration in cycles]
  l1d_pend_miss.pending_cycles                      
       [Cycles with L1D load Misses outstanding]
  l1d_pend_miss.pending_cycles_any                  
       [Cycles with L1D load Misses outstanding from any thread on physical
        core]
  l2_demand_rqsts.wb_hit                            
       [Not rejected writebacks that hit L2 cache]
  l2_lines_in.all                                   
       [L2 cache lines filling L2]
  l2_lines_in.e                                     
       [L2 cache lines in E state filling L2]
  l2_lines_in.i                                     
       [L2 cache lines in I state filling L2]
  l2_lines_in.s                                     
       [L2 cache lines in S state filling L2]
  l2_lines_out.demand_clean                         
       [Clean L2 cache lines evicted by demand]
  l2_rqsts.all_code_rd                              
       [L2 code requests]
  l2_rqsts.all_demand_data_rd                       
       [Demand Data Read requests]
  l2_rqsts.all_demand_miss                          
       [Demand requests that miss L2 cache]
  l2_rqsts.all_demand_references                    
       [Demand requests to L2 cache]
  l2_rqsts.all_pf                                   
       [Requests from L2 hardware prefetchers]
  l2_rqsts.all_rfo                                  
       [RFO requests to L2 cache]
  l2_rqsts.code_rd_hit                              
       [L2 cache hits when fetching instructions, code reads]
  l2_rqsts.code_rd_miss                             
       [L2 cache misses when fetching instructions]
  l2_rqsts.demand_data_rd_hit                       
       [Demand Data Read requests that hit L2 cache]
  l2_rqsts.demand_data_rd_miss                      
       [Demand Data Read miss L2, no rejects]
  l2_rqsts.l2_pf_hit                                
       [L2 prefetch requests that hit L2 cache]
  l2_rqsts.l2_pf_miss                               
       [L2 prefetch requests that miss L2 cache]
  l2_rqsts.miss                                     
       [All requests that miss L2 cache]
  l2_rqsts.references                               
       [All L2 requests]
  l2_rqsts.rfo_hit                                  
       [RFO requests that hit L2 cache]
  l2_rqsts.rfo_miss                                 
       [RFO requests that miss L2 cache]
  l2_trans.all_pf                                   
       [L2 or L3 HW prefetches that access L2 cache]
  l2_trans.all_requests                             
       [Transactions accessing L2 pipe]
  l2_trans.code_rd                                  
       [L2 cache accesses when fetching instructions]
  l2_trans.demand_data_rd                           
       [Demand Data Read requests that access L2 cache]
  l2_trans.l1d_wb                                   
       [L1D writebacks that access L2 cache]
  l2_trans.l2_fill                                  
       [L2 fill requests that access L2 cache]
  l2_trans.l2_wb                                    
       [L2 writebacks that access L2 cache]
  l2_trans.rfo                                      
       [RFO requests that access L2 cache]
  lock_cycles.cache_lock_duration                   
       [Cycles when L1D is locked]
  longest_lat_cache.miss                            
       [Core-originated cacheable demand requests missed L3]
  longest_lat_cache.reference                       
       [Core-originated cacheable demand requests that refer to L3]
  mem_load_uops_l3_hit_retired.xsnp_hit             
       [Retired load uops which data sources were L3 and cross-core snoop hits
        in on-pkg core cache Supports address when precise. Spec update:
        BDM100 (Precise event)]
  mem_load_uops_l3_hit_retired.xsnp_hitm            
       [Retired load uops which data sources were HitM responses from shared
        L3 Supports address when precise. Spec update: BDM100 (Precise event)]
  mem_load_uops_l3_hit_retired.xsnp_miss            
       [Retired load uops which data sources were L3 hit and cross-core snoop
        missed in on-pkg core cache Supports address when precise. Spec
        update: BDM100 (Precise event)]
  mem_load_uops_l3_hit_retired.xsnp_none            
       [Retired load uops which data sources were hits in L3 without snoops
        required Supports address when precise. Spec update: BDM100 (Precise
        event)]
  mem_load_uops_l3_miss_retired.local_dram          
       [Data from local DRAM either Snoop not needed or Snoop Miss (RspI)
        Supports address when precise. Spec update: BDE70, BDM100 (Precise
        event)]
  mem_load_uops_l3_miss_retired.remote_dram         
       [Retired load uop whose Data Source was: remote DRAM either Snoop not
        needed or Snoop Miss (RspI) Supports address when precise. Spec
        update: BDE70 (Precise event)]
  mem_load_uops_l3_miss_retired.remote_fwd          
       [Retired load uop whose Data Source was: forwarded from remote cache
        Supports address when precise. Spec update: BDE70 (Precise event)]
  mem_load_uops_l3_miss_retired.remote_hitm         
       [Retired load uop whose Data Source was: Remote cache HITM Supports
        address when precise. Spec update: BDE70 (Precise event)]
  mem_load_uops_retired.hit_lfb                     
       [Retired load uops which data sources were load uops missed L1 but hit
        FB due to preceding miss to the same cache line with data not ready
        Supports address when precise (Precise event)]
  mem_load_uops_retired.l1_hit                      
       [Retired load uops with L1 cache hits as data sources Supports address
        when precise (Precise event)]
  mem_load_uops_retired.l1_miss                     
       [Retired load uops misses in L1 cache as data sources Supports address
        when precise (Precise event)]
  mem_load_uops_retired.l2_hit                      
       [Retired load uops with L2 cache hits as data sources Supports address
        when precise. Spec update: BDM35 (Precise event)]
  mem_load_uops_retired.l2_miss                     
       [Miss in mid-level (L2) cache. Excludes Unknown data-source Supports
        address when precise (Precise event)]
  mem_load_uops_retired.l3_hit                      
       [Retired load uops which data sources were data hits in L3 without
        snoops required Supports address when precise. Spec update: BDM100
        (Precise event)]
  mem_load_uops_retired.l3_miss                     
       [Miss in last-level (L3) cache. Excludes Unknown data-source Supports
        address when precise. Spec update: BDM100, BDE70 (Precise event)]
  mem_uops_retired.all_loads                        
       [All retired load uops Supports address when precise (Precise event)]
  mem_uops_retired.all_stores                       
       [All retired store uops Supports address when precise (Precise event)]
  mem_uops_retired.lock_loads                       
       [Retired load uops with locked access Supports address when precise.
        Spec update: BDM35 (Precise event)]
  mem_uops_retired.split_loads                      
       [Retired load uops that split across a cacheline boundary Supports
        address when precise (Precise event)]
  mem_uops_retired.split_stores                     
       [Retired store uops that split across a cacheline boundary Supports
        address when precise (Precise event)]
  mem_uops_retired.stlb_miss_loads                  
       [Retired load uops that miss the STLB Supports address when precise
        (Precise event)]
  mem_uops_retired.stlb_miss_stores                 
       [Retired store uops that miss the STLB Supports address when precise
        (Precise event)]
  offcore_requests.all_data_rd                      
       [Demand and prefetch data reads]
  offcore_requests.demand_code_rd                   
       [Cacheable and noncachaeble code read requests]
  offcore_requests.demand_data_rd                   
       [Demand Data Read requests sent to uncore]
  offcore_requests.demand_rfo                       
       [Demand RFO requests including regular RFOs, locks, ItoM]
  offcore_requests_buffer.sq_full                   
       [Offcore requests buffer cannot take more entries for this thread core]
  offcore_requests_outstanding.all_data_rd          
       [Offcore outstanding cacheable Core Data Read transactions in
        SuperQueue (SQ), queue to uncore Spec update: BDM76]
  offcore_requests_outstanding.cycles_with_data_rd  
       [Cycles when offcore outstanding cacheable Core Data Read transactions
        are present in SuperQueue (SQ), queue to uncore Spec update: BDM76]
  offcore_requests_outstanding.cycles_with_demand_data_rd
       [Cycles when offcore outstanding Demand Data Read transactions are
        present in SuperQueue (SQ), queue to uncore Spec update: BDM76]
  offcore_requests_outstanding.cycles_with_demand_rfo
       [Offcore outstanding demand rfo reads transactions in SuperQueue (SQ),
        queue to uncore, every cycle Spec update: BDM76]
  offcore_requests_outstanding.demand_code_rd       
       [Offcore outstanding code reads transactions in SuperQueue (SQ), queue
        to uncore, every cycle Spec update: BDM76]
  offcore_requests_outstanding.demand_data_rd       
       [Offcore outstanding Demand Data Read transactions in uncore queue Spec
        update: BDM76]
  offcore_requests_outstanding.demand_data_rd_ge_6  
       [Cycles with at least 6 offcore outstanding Demand Data Read
        transactions in uncore queue Spec update: BDM76]
  offcore_requests_outstanding.demand_rfo           
       [Offcore outstanding RFO store transactions in SuperQueue (SQ), queue
        to uncore Spec update: BDM76]
  offcore_response                                  
       [Offcore response can be programmed only with a specific pair of event
        select and counter MSR, and with specific event codes and predefine
        mask bit value in a dedicated MSR to specify attributes of the offcore
        transaction]
  offcore_response.all_code_rd.llc_hit.hit_other_core_no_fwd
       [Counts all demand & prefetch code reads that hit in the L3 and the
        snoops to sibling cores hit in either E/S state and the line is not
        forwarded]
  offcore_response.all_data_rd.llc_hit.hit_other_core_no_fwd
       [Counts all demand & prefetch data reads that hit in the L3 and the
        snoops to sibling cores hit in either E/S state and the line is not
        forwarded]
  offcore_response.all_data_rd.llc_hit.hitm_other_core
       [Counts all demand & prefetch data reads that hit in the L3 and the
        snoop to one of the sibling cores hits the line in M state and the
        line is forwarded]
  offcore_response.all_reads.llc_hit.hit_other_core_no_fwd
       [Counts all data/code/rfo reads (demand & prefetch) that hit in the L3
        and the snoops to sibling cores hit in either E/S state and the line
        is not forwarded]
  offcore_response.all_reads.llc_hit.hitm_other_core
       [Counts all data/code/rfo reads (demand & prefetch) that hit in the L3
        and the snoop to one of the sibling cores hits the line in M state and
        the line is forwarded]
  offcore_response.all_requests.llc_hit.any_response
       [Counts all requests that hit in the L3]
  offcore_response.all_rfo.llc_hit.hit_other_core_no_fwd
       [Counts all demand & prefetch RFOs that hit in the L3 and the snoops to
        sibling cores hit in either E/S state and the line is not forwarded]
  offcore_response.all_rfo.llc_hit.hitm_other_core  
       [Counts all demand & prefetch RFOs that hit in the L3 and the snoop to
        one of the sibling cores hits the line in M state and the line is
        forwarded]
  offcore_response.demand_rfo.llc_hit.hitm_other_core
       [Counts all demand data writes (RFOs) that hit in the L3 and the snoop
        to one of the sibling cores hits the line in M state and the line is
        forwarded]
  offcore_response.pf_llc_code_rd.llc_hit.any_response
       [Counts prefetch (that bring data to LLC only) code reads that hit in
        the L3]
  offcore_response.pf_llc_rfo.llc_hit.any_response  
       [Counts all prefetch (that bring data to LLC only) RFOs that hit in the
        L3]
  sq_misc.split_lock                                
       [Split locks in SQ]

floating point:
  fp_arith_inst_retired.128b_packed_double          
       [Number of SSE/AVX computational 128-bit packed double precision
        floating-point instructions retired. Each count represents 2
        computations. Applies to SSE* and AVX* packed double precision
        floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP
        FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they
        perform multiple calculations per element (Precise event)]
  fp_arith_inst_retired.128b_packed_single          
       [Number of SSE/AVX computational 128-bit packed single precision
        floating-point instructions retired. Each count represents 4
        computations. Applies to SSE* and AVX* packed single precision
        floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT
        DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as
        they perform multiple calculations per element (Precise event)]
  fp_arith_inst_retired.256b_packed_double          
       [Number of SSE/AVX computational 256-bit packed double precision
        floating-point instructions retired. Each count represents 4
        computations. Applies to SSE* and AVX* packed double precision
        floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP
        FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they
        perform multiple calculations per element (Precise event)]
  fp_arith_inst_retired.256b_packed_single          
       [Number of SSE/AVX computational 256-bit packed single precision
        floating-point instructions retired. Each count represents 8
        computations. Applies to SSE* and AVX* packed single precision
        floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT
        DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as
        they perform multiple calculations per element (Precise event)]
  fp_arith_inst_retired.double                      
       [Number of SSE/AVX computational double precision floating-point
        instructions retired. Applies to SSE* and AVX*scalar, double and
        single precision floating-point: ADD SUB MUL DIV MIN MAX SQRT DPP
        FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they
        perform multiple calculations per element. ?]
  fp_arith_inst_retired.packed                      
       [Number of SSE/AVX computational packed floating-point instructions
        retired. Applies to SSE* and AVX*, packed, double and single precision
        floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT DPP
        FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they
        perform multiple calculations per element]
  fp_arith_inst_retired.scalar                      
       [Number of SSE/AVX computational scalar floating-point instructions
        retired. Applies to SSE* and AVX* scalar, double and single precision
        floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT FM(N)ADD/SUB.
        FM(N)ADD/SUB instructions count twice as they perform multiple
        calculations per element]
  fp_arith_inst_retired.scalar_double               
       [Number of SSE/AVX computational scalar double precision floating-point
        instructions retired. Each count represents 1 computation. Applies to
        SSE* and AVX* scalar double precision floating-point instructions: ADD
        SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count
        twice as they perform multiple calculations per element (Precise
        event)]
  fp_arith_inst_retired.scalar_single               
       [Number of SSE/AVX computational scalar single precision floating-point
        instructions retired. Each count represents 1 computation. Applies to
        SSE* and AVX* scalar single precision floating-point instructions: ADD
        SUB MUL DIV MIN MAX RCP RSQRT SQRT FM(N)ADD/SUB. FM(N)ADD/SUB
        instructions count twice as they perform multiple calculations per
        element (Precise event)]
  fp_arith_inst_retired.single                      
       [Number of SSE/AVX computational single precision floating-point
        instructions retired. Applies to SSE* and AVX*scalar, double and
        single precision floating-point: ADD SUB MUL DIV MIN MAX RCP RSQRT
        SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice
        as they perform multiple calculations per element. ?]
  fp_assist.any                                     
       [Cycles with any input/output SSE or FP assist]
  fp_assist.simd_input                              
       [Number of SIMD FP assists due to input values]
  fp_assist.simd_output                             
       [Number of SIMD FP assists due to Output values]
  fp_assist.x87_input                               
       [Number of X87 assists due to input value]
  fp_assist.x87_output                              
       [Number of X87 assists due to output value]
  other_assists.avx_to_sse                          
       [Number of transitions from AVX-256 to legacy SSE when penalty
        applicable Spec update: BDM30]
  other_assists.sse_to_avx                          
       [Number of transitions from SSE to AVX-256 when penalty applicable Spec
        update: BDM30]

frontend:
  dsb2mite_switches.penalty_cycles                  
       [Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles]
  icache.hit                                        
       [Number of Instruction Cache, Streaming Buffer and Victim Cache Reads.
        both cacheable and noncacheable, including UC fetches]
  icache.ifdata_stall                               
       [Cycles where a code fetch is stalled due to L1 instruction-cache miss]
  icache.misses                                     
       [Number of Instruction Cache, Streaming Buffer and Victim Cache Misses.
        Includes Uncacheable accesses]
  idq.all_dsb_cycles_4_uops                         
       [Cycles Decode Stream Buffer (DSB) is delivering 4 Uops]
  idq.all_dsb_cycles_any_uops                       
       [Cycles Decode Stream Buffer (DSB) is delivering any Uop]
  idq.all_mite_cycles_4_uops                        
       [Cycles MITE is delivering 4 Uops]
  idq.all_mite_cycles_any_uops                      
       [Cycles MITE is delivering any Uop]
  idq.dsb_cycles                                    
       [Cycles when uops are being delivered to Instruction Decode Queue (IDQ)
        from Decode Stream Buffer (DSB) path]
  idq.dsb_uops                                      
       [Uops delivered to Instruction Decode Queue (IDQ) from the Decode
        Stream Buffer (DSB) path]
  idq.empty                                         
       [Instruction Decode Queue (IDQ) empty cycles]
  idq.mite_all_uops                                 
       [Uops delivered to Instruction Decode Queue (IDQ) from MITE path]
  idq.mite_cycles                                   
       [Cycles when uops are being delivered to Instruction Decode Queue (IDQ)
        from MITE path]
  idq.mite_uops                                     
       [Uops delivered to Instruction Decode Queue (IDQ) from MITE path]
  idq.ms_cycles                                     
       [Cycles when uops are being delivered to Instruction Decode Queue (IDQ)
        while Microcode Sequenser (MS) is busy]
  idq.ms_dsb_cycles                                 
       [Cycles when uops initiated by Decode Stream Buffer (DSB) are being
        delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser
        (MS) is busy]
  idq.ms_dsb_occur                                  
       [Deliveries to Instruction Decode Queue (IDQ) initiated by Decode
        Stream Buffer (DSB) while Microcode Sequenser (MS) is busy]
  idq.ms_dsb_uops                                   
       [Uops initiated by Decode Stream Buffer (DSB) that are being delivered
        to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is
        busy]
  idq.ms_mite_uops                                  
       [Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ)
        while Microcode Sequenser (MS) is busy]
  idq.ms_switches                                   
       [Number of switches from DSB (Decode Stream Buffer) or MITE (legacy
        decode pipeline) to the Microcode Sequencer]
  idq.ms_uops                                       
       [Uops delivered to Instruction Decode Queue (IDQ) while Microcode
        Sequenser (MS) is busy]
  idq_uops_not_delivered.core                       
       [Uops not delivered to Resource Allocation Table (RAT) per thread when
        backend of the machine is not stalled]
  idq_uops_not_delivered.cycles_0_uops_deliv.core   
       [Cycles per thread when 4 or more uops are not delivered to Resource
        Allocation Table (RAT) when backend of the machine is not stalled]
  idq_uops_not_delivered.cycles_fe_was_ok           
       [Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT)
        was stalling FE]
  idq_uops_not_delivered.cycles_le_1_uop_deliv.core 
       [Cycles per thread when 3 or more uops are not delivered to Resource
        Allocation Table (RAT) when backend of the machine is not stalled]
  idq_uops_not_delivered.cycles_le_2_uop_deliv.core 
       [Cycles with less than 2 uops delivered by the front end]
  idq_uops_not_delivered.cycles_le_3_uop_deliv.core 
       [Cycles with less than 3 uops delivered by the front end]

memory:
  hle_retired.aborted                               
       [Number of times HLE abort was triggered (Precise event)]
  hle_retired.aborted_misc1                         
       [Number of times an HLE execution aborted due to various memory events
        (e.g., read/write capacity and conflicts)]
  hle_retired.aborted_misc2                         
       [Number of times an HLE execution aborted due to uncommon conditions]
  hle_retired.aborted_misc3                         
       [Number of times an HLE execution aborted due to HLE-unfriendly
        instructions]
  hle_retired.aborted_misc4                         
       [Number of times an HLE execution aborted due to incompatible memory
        type]
  hle_retired.aborted_misc5                         
       [Number of times an HLE execution aborted due to none of the previous 4
        categories (e.g. interrupts)]
  hle_retired.commit                                
       [Number of times HLE commit succeeded]
  hle_retired.start                                 
       [Number of times we entered an HLE region; does not count nested
        transactions]
  machine_clears.memory_ordering                    
       [Counts the number of machine clears due to memory order conflicts]
  mem_trans_retired.load_latency_gt_128             
       [Loads with latency value being above 128 Spec update: BDM100, BDM35
        (Must be precise)]
  mem_trans_retired.load_latency_gt_16              
       [Loads with latency value being above 16 Spec update: BDM100, BDM35
        (Must be precise)]
  mem_trans_retired.load_latency_gt_256             
       [Loads with latency value being above 256 Spec update: BDM100, BDM35
        (Must be precise)]
  mem_trans_retired.load_latency_gt_32              
       [Loads with latency value being above 32 Spec update: BDM100, BDM35
        (Must be precise)]
  mem_trans_retired.load_latency_gt_4               
       [Loads with latency value being above 4 Spec update: BDM100, BDM35
        (Must be precise)]
  mem_trans_retired.load_latency_gt_512             
       [Loads with latency value being above 512 Spec update: BDM100, BDM35
        (Must be precise)]
  mem_trans_retired.load_latency_gt_64              
       [Loads with latency value being above 64 Spec update: BDM100, BDM35
        (Must be precise)]
  mem_trans_retired.load_latency_gt_8               
       [Loads with latency value being above 8 Spec update: BDM100, BDM35
        (Must be precise)]
  misalign_mem_ref.loads                            
       [Speculative cache line split load uops dispatched to L1 cache]
  misalign_mem_ref.stores                           
       [Speculative cache line split STA uops dispatched to L1 cache]
  offcore_response.all_code_rd.llc_miss.any_response
       [Counts all demand & prefetch code reads that miss in the L3]
  offcore_response.all_code_rd.llc_miss.local_dram  
       [Counts all demand & prefetch code reads that miss the L3 and the data
        is returned from local dram]
  offcore_response.all_data_rd.llc_miss.any_response
       [Counts all demand & prefetch data reads that miss in the L3]
  offcore_response.all_data_rd.llc_miss.local_dram  
       [Counts all demand & prefetch data reads that miss the L3 and the data
        is returned from local dram]
  offcore_response.all_data_rd.llc_miss.remote_dram 
       [Counts all demand & prefetch data reads that miss the L3 and the data
        is returned from remote dram]
  offcore_response.all_data_rd.llc_miss.remote_hit_forward
       [Counts all demand & prefetch data reads that miss the L3 and clean or
        shared data is transferred from remote cache]
  offcore_response.all_data_rd.llc_miss.remote_hitm 
       [Counts all demand & prefetch data reads that miss the L3 and the
        modified data is transferred from remote cache]
  offcore_response.all_reads.llc_miss.any_response  
       [Counts all data/code/rfo reads (demand & prefetch) that miss in the L3]
  offcore_response.all_reads.llc_miss.local_dram    
       [Counts all data/code/rfo reads (demand & prefetch) that miss the L3
        and the data is returned from local dram]
  offcore_response.all_reads.llc_miss.remote_dram   
       [Counts all data/code/rfo reads (demand & prefetch) that miss the L3
        and the data is returned from remote dram]
  offcore_response.all_reads.llc_miss.remote_hit_forward
       [Counts all data/code/rfo reads (demand & prefetch) that miss the L3
        and clean or shared data is transferred from remote cache]
  offcore_response.all_reads.llc_miss.remote_hitm   
       [Counts all data/code/rfo reads (demand & prefetch) that miss the L3
        and the modified data is transferred from remote cache]
  offcore_response.all_requests.llc_miss.any_response
       [Counts all requests that miss in the L3]
  offcore_response.all_rfo.llc_miss.any_response    
       [Counts all demand & prefetch RFOs that miss in the L3]
  offcore_response.all_rfo.llc_miss.local_dram      
       [Counts all demand & prefetch RFOs that miss the L3 and the data is
        returned from local dram]
  offcore_response.demand_rfo.llc_miss.remote_hitm  
       [Counts all demand data writes (RFOs) that miss the L3 and the modified
        data is transferred from remote cache]
  offcore_response.pf_llc_code_rd.llc_miss.any_response
       [Counts prefetch (that bring data to LLC only) code reads that miss in
        the L3]
  offcore_response.pf_llc_rfo.llc_miss.any_response 
       [Counts all prefetch (that bring data to LLC only) RFOs that miss in
        the L3]
  rtm_retired.aborted                               
       [Number of times RTM abort was triggered (Precise event)]
  rtm_retired.aborted_misc1                         
       [Number of times an RTM execution aborted due to various memory events
        (e.g. read/write capacity and conflicts)]
  rtm_retired.aborted_misc2                         
       [Number of times an RTM execution aborted due to various memory events
        (e.g., read/write capacity and conflicts)]
  rtm_retired.aborted_misc3                         
       [Number of times an RTM execution aborted due to HLE-unfriendly
        instructions]
  rtm_retired.aborted_misc4                         
       [Number of times an RTM execution aborted due to incompatible memory
        type]
  rtm_retired.aborted_misc5                         
       [Number of times an RTM execution aborted due to none of the previous 4
        categories (e.g. interrupt)]
  rtm_retired.commit                                
       [Number of times RTM commit succeeded]
  rtm_retired.start                                 
       [Number of times we entered an RTM region; does not count nested
        transactions]
  tx_exec.misc1                                     
       [Counts the number of times a class of instructions that may cause a
        transactional abort was executed. Since this is the count of
        execution, it may not always cause a transactional abort]
  tx_exec.misc2                                     
       [Counts the number of times a class of instructions (e.g., vzeroupper)
        that may cause a transactional abort was executed inside a
        transactional region]
  tx_exec.misc3                                     
       [Counts the number of times an instruction execution caused the
        transactional nest count supported to be exceeded]
  tx_exec.misc4                                     
       [Counts the number of times a XBEGIN instruction was executed inside an
        HLE transactional region]
  tx_exec.misc5                                     
       [Counts the number of times an HLE XACQUIRE instruction was executed
        inside an RTM transactional region]
  tx_mem.abort_capacity_write                       
       [Number of times a TSX Abort was triggered due to an evicted line
        caused by a transaction overflow]
  tx_mem.abort_conflict                             
       [Number of times a TSX line had a cache conflict]
  tx_mem.abort_hle_elision_buffer_mismatch          
       [Number of times a TSX Abort was triggered due to release/commit but
        data and address mismatch]
  tx_mem.abort_hle_elision_buffer_not_empty         
       [Number of times a TSX Abort was triggered due to commit but Lock
        Buffer not empty]
  tx_mem.abort_hle_elision_buffer_unsupported_alignment
       [Number of times a TSX Abort was triggered due to attempting an
        unsupported alignment from Lock Buffer]
  tx_mem.abort_hle_store_to_elided_lock             
       [Number of times a TSX Abort was triggered due to a non-release/commit
        store to lock]
  tx_mem.hle_elision_buffer_full                    
       [Number of times we could not allocate Lock Buffer]

other:
  cpl_cycles.ring0                                  
       [Unhalted core cycles when the thread is in ring 0]
  cpl_cycles.ring0_trans                            
       [Number of intervals between processor halts while thread is in ring 0]
  cpl_cycles.ring123                                
       [Unhalted core cycles when thread is in rings 1, 2, or 3]
  lock_cycles.split_lock_uc_lock_duration           
       [Cycles when L1 and L2 are locked due to UC or split lock]

pipeline:
  arith.fpu_div_active                              
       [Cycles when divider is busy executing divide operations]
  baclears.any                                      
       [Counts the total number when the front end is resteered, mainly when
        the BPU cannot provide a correct prediction and this is corrected by
        other branch handling mechanisms at the front end]
  br_inst_exec.all_branches                         
       [Speculative and retired branches]
  br_inst_exec.all_conditional                      
       [Speculative and retired macro-conditional branches]
  br_inst_exec.all_direct_jmp                       
       [Speculative and retired macro-unconditional branches excluding calls
        and indirects]
  br_inst_exec.all_direct_near_call                 
       [Speculative and retired direct near calls]
  br_inst_exec.all_indirect_jump_non_call_ret       
       [Speculative and retired indirect branches excluding calls and returns]
  br_inst_exec.all_indirect_near_return             
       [Speculative and retired indirect return branches]
  br_inst_exec.nontaken_conditional                 
       [Not taken macro-conditional branches]
  br_inst_exec.taken_conditional                    
       [Taken speculative and retired macro-conditional branches]
  br_inst_exec.taken_direct_jump                    
       [Taken speculative and retired macro-conditional branch instructions
        excluding calls and indirects]
  br_inst_exec.taken_direct_near_call               
       [Taken speculative and retired direct near calls]
  br_inst_exec.taken_indirect_jump_non_call_ret     
       [Taken speculative and retired indirect branches excluding calls and
        returns]
  br_inst_exec.taken_indirect_near_call             
       [Taken speculative and retired indirect calls]
  br_inst_exec.taken_indirect_near_return           
       [Taken speculative and retired indirect branches with return mnemonic]
  br_inst_retired.all_branches                      
       [All (macro) branch instructions retired]
  br_inst_retired.all_branches_pebs                 
       [All (macro) branch instructions retired. (Precise Event - PEBS) Spec
        update: BDW98 (Must be precise)]
  br_inst_retired.conditional                       
       [Conditional branch instructions retired (Precise event)]
  br_inst_retired.far_branch                        
       [Far branch instructions retired Spec update: BDW98]
  br_inst_retired.near_call                         
       [Direct and indirect near call instructions retired (Precise event)]
  br_inst_retired.near_return                       
       [Return instructions retired (Precise event)]
  br_inst_retired.near_taken                        
       [Taken branch instructions retired (Precise event)]
  br_inst_retired.not_taken                         
       [Not taken branch instructions retired]
  br_misp_exec.all_branches                         
       [Speculative and retired mispredicted macro conditional branches]
  br_misp_exec.all_conditional                      
       [Speculative and retired mispredicted macro conditional branches]
  br_misp_exec.all_indirect_jump_non_call_ret       
       [Mispredicted indirect branches excluding calls and returns]
  br_misp_exec.nontaken_conditional                 
       [Not taken speculative and retired mispredicted macro conditional
        branches]
  br_misp_exec.taken_conditional                    
       [Taken speculative and retired mispredicted macro conditional branches]
  br_misp_exec.taken_indirect_jump_non_call_ret     
       [Taken speculative and retired mispredicted indirect branches excluding
        calls and returns]
  br_misp_exec.taken_indirect_near_call             
       [Taken speculative and retired mispredicted indirect calls]
  br_misp_exec.taken_return_near                    
       [Taken speculative and retired mispredicted indirect branches with
        return mnemonic]
  br_misp_retired.all_branches                      
       [All mispredicted macro branch instructions retired]
  br_misp_retired.all_branches_pebs                 
       [Mispredicted macro branch instructions retired. (Precise Event - PEBS)
        (Must be precise)]
  br_misp_retired.conditional                       
       [Mispredicted conditional branch instructions retired (Precise event)]
  br_misp_retired.near_taken                        
       [number of near branch instructions retired that were mispredicted and
        taken (Precise event)]
  br_misp_retired.ret                               
       [This event counts the number of mispredicted ret instructions retired.
        Non PEBS (Precise event)]
  cpu_clk_thread_unhalted.one_thread_active         
       [Count XClk pulses when this thread is unhalted and the other thread is
        halted]
  cpu_clk_thread_unhalted.ref_xclk                  
       [Reference cycles when the thread is unhalted (counts at 100 MHz rate)]
  cpu_clk_thread_unhalted.ref_xclk_any              
       [Reference cycles when the at least one thread on the physical core is
        unhalted (counts at 100 MHz rate)]
  cpu_clk_unhalted.one_thread_active                
       [Count XClk pulses when this thread is unhalted and the other thread is
        halted]
  cpu_clk_unhalted.ref_tsc                          
       [Reference cycles when the core is not in halt state]
  cpu_clk_unhalted.ref_xclk                         
       [Reference cycles when the thread is unhalted (counts at 100 MHz rate)]
  cpu_clk_unhalted.ref_xclk_any                     
       [Reference cycles when the at least one thread on the physical core is
        unhalted (counts at 100 MHz rate)]
  cpu_clk_unhalted.thread                           
       [Core cycles when the thread is not in halt state]
  cpu_clk_unhalted.thread_any                       
       [Core cycles when at least one thread on the physical core is not in
        halt state]
  cpu_clk_unhalted.thread_p                         
       [Thread cycles when thread is not in halt state]
  cpu_clk_unhalted.thread_p_any                     
       [Core cycles when at least one thread on the physical core is not in
        halt state]
  cycle_activity.cycles_l1d_miss                    
       [Cycles while L1 cache miss demand load is outstanding]
  cycle_activity.cycles_l1d_pending                 
       [Cycles while L1 cache miss demand load is outstanding]
  cycle_activity.cycles_l2_miss                     
       [Cycles while L2 cache miss demand load is outstanding]
  cycle_activity.cycles_l2_pending                  
       [Cycles while L2 cache miss demand load is outstanding]
  cycle_activity.cycles_ldm_pending                 
       [Cycles while memory subsystem has an outstanding load]
  cycle_activity.cycles_mem_any                     
       [Cycles while memory subsystem has an outstanding load]
  cycle_activity.cycles_no_execute                  
       [Total execution stalls]
  cycle_activity.stalls_l1d_miss                    
       [Execution stalls while L1 cache miss demand load is outstanding]
  cycle_activity.stalls_l1d_pending                 
       [Execution stalls while L1 cache miss demand load is outstanding]
  cycle_activity.stalls_l2_miss                     
       [Execution stalls while L2 cache miss demand load is outstanding]
  cycle_activity.stalls_l2_pending                  
       [Execution stalls while L2 cache miss demand load is outstanding]
  cycle_activity.stalls_ldm_pending                 
       [Execution stalls while memory subsystem has an outstanding load]
  cycle_activity.stalls_mem_any                     
       [Execution stalls while memory subsystem has an outstanding load]
  cycle_activity.stalls_total                       
       [Total execution stalls]
  ild_stall.lcp                                     
       [Stalls caused by changing prefix length of the instruction]
  inst_retired.any                                  
       [Instructions retired from execution]
  inst_retired.any_p                                
       [Number of instructions retired. General Counter - architectural event
        Spec update: BDM61]
  inst_retired.prec_dist                            
       [Precise instruction retired event with HW to reduce effect of PEBS
        shadow in IP distribution Spec update: BDM11, BDM55 (Must be precise)]
  inst_retired.x87                                  
       [FP operations retired. X87 FP operations that have no exceptions:]
  int_misc.rat_stall_cycles                         
       [Cycles when Resource Allocation Table (RAT) external stall is sent to
        Instruction Decode Queue (IDQ) for the thread]
  int_misc.recovery_cycles                          
       [Number of cycles waiting for the checkpoints in Resource Allocation
        Table (RAT) to be recovered after Nuke due to all other cases except
        JEClear (e.g. whenever a ucode assist is needed like SSE exception,
        memory disambiguation, etc...)]
  int_misc.recovery_cycles_any                      
       [Core cycles the allocator was stalled due to recovery from earlier
        clear event for any thread running on the physical core (e.g.
        misprediction or memory nuke)]
  ld_blocks.no_sr                                   
       [This event counts the number of times that split load operations are
        temporarily blocked because all resources for handling the split
        accesses are in use]
  ld_blocks.store_forward                           
       [Cases when loads get true Block-on-Store blocking code preventing
        store forwarding]
  ld_blocks_partial.address_alias                   
       [False dependencies in MOB due to partial compare]
  load_hit_pre.hw_pf                                
       [Not software-prefetch load dispatches that hit FB allocated for
        hardware prefetch]
  load_hit_pre.sw_pf                                
       [Not software-prefetch load dispatches that hit FB allocated for
        software prefetch]
  lsd.cycles_4_uops                                 
       [Cycles 4 Uops delivered by the LSD, but didn't come from the decoder]
  lsd.cycles_active                                 
       [Cycles Uops delivered by the LSD, but didn't come from the decoder]
  lsd.uops                                          
       [Number of Uops delivered by the LSD]
  machine_clears.count                              
       [Number of machine clears (nukes) of any type]
  machine_clears.cycles                             
       [Cycles there was a Nuke. Account for both thread-specific and All
        Thread Nukes]
  machine_clears.maskmov                            
       [This event counts the number of executed Intel AVX masked load
        operations that refer to an illegal address range with the mask bits
        set to 0]
  machine_clears.smc                                
       [Self-modifying code (SMC) detected]
  move_elimination.int_eliminated                   
       [Number of integer Move Elimination candidate uops that were eliminated]
  move_elimination.int_not_eliminated               
       [Number of integer Move Elimination candidate uops that were not
        eliminated]
  move_elimination.simd_eliminated                  
       [Number of SIMD Move Elimination candidate uops that were eliminated]
  move_elimination.simd_not_eliminated              
       [Number of SIMD Move Elimination candidate uops that were not
        eliminated]
  other_assists.any_wb_assist                       
       [Number of times any microcode assist is invoked by HW upon uop
        writeback]
  resource_stalls.any                               
       [Resource-related stall cycles]
  resource_stalls.rob                               
       [Cycles stalled due to re-order buffer full]
  resource_stalls.rs                                
       [Cycles stalled due to no eligible RS entry available]
  resource_stalls.sb                                
       [Cycles stalled due to no store buffers available. (not including
        draining form sync)]
  rob_misc_events.lbr_inserts                       
       [Count cases of saving new LBR]
  rs_events.empty_cycles                            
       [Cycles when Reservation Station (RS) is empty for the thread]
  rs_events.empty_end                               
       [Counts end of periods where the Reservation Station (RS) was empty.
        Could be useful to precisely locate Frontend Latency Bound issues]
  uop_dispatches_cancelled.simd_prf                 
       [Micro-op dispatches cancelled due to insufficient SIMD physical
        register file read ports]
  uops_dispatched_port.port_0                       
       [Cycles per thread when uops are executed in port 0]
  uops_dispatched_port.port_1                       
       [Cycles per thread when uops are executed in port 1]
  uops_dispatched_port.port_2                       
       [Cycles per thread when uops are executed in port 2]
  uops_dispatched_port.port_3                       
       [Cycles per thread when uops are executed in port 3]
  uops_dispatched_port.port_4                       
       [Cycles per thread when uops are executed in port 4]
  uops_dispatched_port.port_5                       
       [Cycles per thread when uops are executed in port 5]
  uops_dispatched_port.port_6                       
       [Cycles per thread when uops are executed in port 6]
  uops_dispatched_port.port_7                       
       [Cycles per thread when uops are executed in port 7]
  uops_executed.core                                
       [Number of uops executed on the core]
  uops_executed.core_cycles_ge_1                    
       [Cycles at least 1 micro-op is executed from any thread on physical
        core]
  uops_executed.core_cycles_ge_2                    
       [Cycles at least 2 micro-op is executed from any thread on physical
        core]
  uops_executed.core_cycles_ge_3                    
       [Cycles at least 3 micro-op is executed from any thread on physical
        core]
  uops_executed.core_cycles_ge_4                    
       [Cycles at least 4 micro-op is executed from any thread on physical
        core]
  uops_executed.core_cycles_none                    
       [Cycles with no micro-ops executed from any thread on physical core]
  uops_executed.cycles_ge_1_uop_exec                
       [Cycles where at least 1 uop was executed per-thread]
  uops_executed.cycles_ge_2_uops_exec               
       [Cycles where at least 2 uops were executed per-thread]
  uops_executed.cycles_ge_3_uops_exec               
       [Cycles where at least 3 uops were executed per-thread]
  uops_executed.cycles_ge_4_uops_exec               
       [Cycles where at least 4 uops were executed per-thread]
  uops_executed.stall_cycles                        
       [Counts number of cycles no uops were dispatched to be executed on this
        thread]
  uops_executed.thread                              
       [Counts the number of uops to be executed per-thread each cycle]
  uops_executed_port.port_0                         
       [Cycles per thread when uops are executed in port 0]
  uops_executed_port.port_0_core                    
       [Cycles per core when uops are exectuted in port 0]
  uops_executed_port.port_1                         
       [Cycles per thread when uops are executed in port 1]
  uops_executed_port.port_1_core                    
       [Cycles per core when uops are exectuted in port 1]
  uops_executed_port.port_2                         
       [Cycles per thread when uops are executed in port 2]
  uops_executed_port.port_2_core                    
       [Cycles per core when uops are dispatched to port 2]
  uops_executed_port.port_3                         
       [Cycles per thread when uops are executed in port 3]
  uops_executed_port.port_3_core                    
       [Cycles per core when uops are dispatched to port 3]
  uops_executed_port.port_4                         
       [Cycles per thread when uops are executed in port 4]
  uops_executed_port.port_4_core                    
       [Cycles per core when uops are exectuted in port 4]
  uops_executed_port.port_5                         
       [Cycles per thread when uops are executed in port 5]
  uops_executed_port.port_5_core                    
       [Cycles per core when uops are exectuted in port 5]
  uops_executed_port.port_6                         
       [Cycles per thread when uops are executed in port 6]
  uops_executed_port.port_6_core                    
       [Cycles per core when uops are exectuted in port 6]
  uops_executed_port.port_7                         
       [Cycles per thread when uops are executed in port 7]
  uops_executed_port.port_7_core                    
       [Cycles per core when uops are dispatched to port 7]
  uops_issued.any                                   
       [Uops that Resource Allocation Table (RAT) issues to Reservation
        Station (RS)]
  uops_issued.flags_merge                           
       [Number of flags-merge uops being allocated. Such uops considered perf
        sensitive; added by GSR u-arch]
  uops_issued.single_mul                            
       [Number of Multiply packed/scalar single precision uops allocated]
  uops_issued.slow_lea                              
       [Number of slow LEA uops being allocated. A uop is generally considered
        SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if
        as a result of LEA instruction or not]
  uops_issued.stall_cycles                          
       [Cycles when Resource Allocation Table (RAT) does not issue Uops to
        Reservation Station (RS) for the thread]
  uops_retired.all                                  
       [Actually retired uops Supports address when precise (Precise event)]
  uops_retired.retire_slots                         
       [Retirement slots used (Precise event)]
  uops_retired.stall_cycles                         
       [Cycles without actually retired uops]
  uops_retired.total_cycles                         
       [Cycles with less than 10 actually retired uops]

uncore cache:
  llc_misses.code_llc_prefetch                      
       [LLC prefetch misses for code reads. Derived from
        unc_c_tor_inserts.miss_opcode. Unit: uncore_cbox]
  llc_misses.data_llc_prefetch                      
       [LLC prefetch misses for data reads. Derived from
        unc_c_tor_inserts.miss_opcode. Unit: uncore_cbox]
  llc_misses.data_read                              
       [LLC misses - demand and prefetch data reads - excludes LLC prefetches.
        Derived from unc_c_tor_inserts.miss_opcode. Unit: uncore_cbox]
  llc_misses.mmio_read                              
       [MMIO reads. Derived from unc_c_tor_inserts.miss_opcode. Unit:
        uncore_cbox]
  llc_misses.mmio_write                             
       [MMIO writes. Derived from unc_c_tor_inserts.miss_opcode. Unit:
        uncore_cbox]
  llc_misses.pcie_non_snoop_write                   
       [PCIe write misses (full cache line). Derived from
        unc_c_tor_inserts.miss_opcode. Unit: uncore_cbox]
  llc_misses.pcie_read                              
       [LLC misses for PCIe read current. Derived from
        unc_c_tor_inserts.miss_opcode. Unit: uncore_cbox]
  llc_misses.pcie_write                             
       [ItoM write misses (as part of fast string memcpy stores) + PCIe full
        line writes. Derived from unc_c_tor_inserts.miss_opcode. Unit:
        uncore_cbox]
  llc_misses.rfo_llc_prefetch                       
       [LLC prefetch misses for RFO. Derived from
        unc_c_tor_inserts.miss_opcode. Unit: uncore_cbox]
  llc_misses.uncacheable                            
       [LLC misses - Uncacheable reads (from cpu) . Derived from
        unc_c_tor_inserts.miss_opcode. Unit: uncore_cbox]
  llc_references.code_llc_prefetch                  
       [L2 demand and L2 prefetch code references to LLC. Derived from
        unc_c_tor_inserts.opcode. Unit: uncore_cbox]
  llc_references.pcie_ns_partial_write              
       [PCIe writes (partial cache line). Derived from
        unc_c_tor_inserts.opcode. Unit: uncore_cbox]
  llc_references.pcie_read                          
       [PCIe read current. Derived from unc_c_tor_inserts.opcode. Unit:
        uncore_cbox]
  llc_references.pcie_write                         
       [PCIe write references (full cache line). Derived from
        unc_c_tor_inserts.opcode. Unit: uncore_cbox]
  llc_references.streaming_full                     
       [Streaming stores (full cache line). Derived from
        unc_c_tor_inserts.opcode. Unit: uncore_cbox]
  llc_references.streaming_partial                  
       [Streaming stores (partial cache line). Derived from
        unc_c_tor_inserts.opcode. Unit: uncore_cbox]
  unc_c_clockticks                                  
       [Uncore cache clock ticks. Unit: uncore_cbox]
  unc_c_llc_lookup.any                              
       [All LLC Misses (code+ data rd + data wr - including demand and
        prefetch). Unit: uncore_cbox]
  unc_c_llc_victims.m_state                         
       [M line evictions from LLC (writebacks to memory). Unit: uncore_cbox]
  unc_c_tor_occupancy.llc_data_read                 
       [Occupancy counter for LLC data reads (demand and L2 prefetch). Derived
        from unc_c_tor_occupancy.miss_opcode. Unit: uncore_cbox]
  unc_h_requests.reads                              
       [read requests to home agent. Unit: uncore_ha]
  unc_h_requests.reads_local                        
       [read requests to local home agent. Unit: uncore_ha]
  unc_h_requests.reads_remote                       
       [read requests to remote home agent. Unit: uncore_ha]
  unc_h_requests.writes                             
       [write requests to home agent. Unit: uncore_ha]
  unc_h_requests.writes_local                       
       [write requests to local home agent. Unit: uncore_ha]
  unc_h_requests.writes_remote                      
       [write requests to remote home agent. Unit: uncore_ha]
  unc_h_snoop_resp.rsp_fwd_wb                       
       [M line forwarded from remote cache along with writeback to memory.
        Unit: uncore_ha]
  unc_h_snoop_resp.rspcnflct                        
       [Conflict requests (requests for same address from multiple agents
        simultaneously). Unit: uncore_ha]
  unc_h_snoop_resp.rspifwd                          
       [M line forwarded from remote cache with no writeback to memory. Unit:
        uncore_ha]
  unc_h_snoop_resp.rsps                             
       [Shared line response from remote cache. Unit: uncore_ha]
  unc_h_snoop_resp.rspsfwd                          
       [Shared line forwarded from remote cache. Unit: uncore_ha]

uncore interconnect:
  qpi_ctl_bandwidth_tx                              
       [Number of non data (control) flits transmitted . Derived from
        unc_q_txl_flits_g0.non_data. Unit: uncore_qpi]
  qpi_data_bandwidth_tx                             
       [Number of data flits transmitted . Derived from
        unc_q_txl_flits_g0.data. Unit: uncore_qpi]
  unc_q_clockticks                                  
       [QPI clock ticks. Unit: uncore_qpi]

uncore memory:
  llc_misses.mem_read                               
       [read requests to memory controller. Derived from unc_m_cas_count.rd.
        Unit: uncore_imc]
  llc_misses.mem_write                              
       [write requests to memory controller. Derived from unc_m_cas_count.wr.
        Unit: uncore_imc]
  unc_m_clockticks                                  
       [Memory controller clock ticks. Unit: uncore_imc]
  unc_m_power_channel_ppd                           
       [Cycles where DRAM ranks are in power down (CKE) mode. Unit: uncore_imc]
  unc_m_power_critical_throttle_cycles              
       [Cycles all ranks are in critical thermal throttle. Unit: uncore_imc]
  unc_m_power_self_refresh                          
       [Cycles Memory is in self refresh power mode. Unit: uncore_imc]
  unc_m_pre_count.page_miss                         
       [Pre-charges due to page misses. Unit: uncore_imc]
  unc_m_pre_count.rd                                
       [Pre-charge for reads. Unit: uncore_imc]
  unc_m_pre_count.wr                                
       [Pre-charge for writes. Unit: uncore_imc]

uncore power:
  unc_p_clockticks                                  
       [PCU clock ticks. Use to get percentages of PCU cycles events. Unit:
        uncore_pcu]
  unc_p_freq_max_limit_thermal_cycles               
       [Counts the number of cycles when temperature is the upper limit on
        frequency. Unit: uncore_pcu]
  unc_p_freq_max_os_cycles                          
       [Counts the number of cycles when the OS is the upper limit on
        frequency. Unit: uncore_pcu]
  unc_p_freq_max_power_cycles                       
       [Counts the number of cycles when power is the upper limit on
        frequency. Unit: uncore_pcu]
  unc_p_freq_trans_cycles                           
       [Counts the number of cycles when current is the upper limit on
        frequency. Unit: uncore_pcu]
  unc_p_power_state_occupancy.cores_c0              
       [This is an occupancy event that tracks the number of cores that are in
        C0. It can be used by itself to get the average number of cores in C0,
        with threshholding to generate histograms, or with other PCU events
        and occupancy triggering to capture other details. Unit: uncore_pcu]
  unc_p_power_state_occupancy.cores_c3              
       [This is an occupancy event that tracks the number of cores that are in
        C3. It can be used by itself to get the average number of cores in C0,
        with threshholding to generate histograms, or with other PCU events
        and occupancy triggering to capture other details. Unit: uncore_pcu]
  unc_p_power_state_occupancy.cores_c6              
       [This is an occupancy event that tracks the number of cores that are in
        C6. It can be used by itself to get the average number of cores in C0,
        with threshholding to generate histograms, or with other PCU events .
        Unit: uncore_pcu]
  unc_p_prochot_external_cycles                     
       [Counts the number of cycles that we are in external PROCHOT mode. This
        mode is triggered when a sensor off the die determines that something
        off-die (like DRAM) is too hot and must throttle to avoid damaging the
        chip. Unit: uncore_pcu]

virtual memory:
  dtlb_load_misses.miss_causes_a_walk               
       [Load misses in all DTLB levels that cause page walks Spec update:
        BDM69]
  dtlb_load_misses.stlb_hit                         
       [Load operations that miss the first DTLB level but hit the second and
        do not cause page walks]
  dtlb_load_misses.stlb_hit_2m                      
       [Load misses that miss the DTLB and hit the STLB (2M)]
  dtlb_load_misses.stlb_hit_4k                      
       [Load misses that miss the DTLB and hit the STLB (4K)]
  dtlb_load_misses.walk_completed                   
       [Demand load Miss in all translation lookaside buffer (TLB) levels
        causes a page walk that completes of any page size Spec update: BDM69]
  dtlb_load_misses.walk_completed_1g                
       [Load miss in all TLB levels causes a page walk that completes. (1G)
        Spec update: BDM69]
  dtlb_load_misses.walk_completed_2m_4m             
       [Demand load Miss in all translation lookaside buffer (TLB) levels
        causes a page walk that completes (2M/4M) Spec update: BDM69]
  dtlb_load_misses.walk_completed_4k                
       [Demand load Miss in all translation lookaside buffer (TLB) levels
        causes a page walk that completes (4K) Spec update: BDM69]
  dtlb_load_misses.walk_duration                    
       [Cycles when PMH is busy with page walks Spec update: BDM69]
  dtlb_store_misses.miss_causes_a_walk              
       [Store misses in all DTLB levels that cause page walks Spec update:
        BDM69]
  dtlb_store_misses.stlb_hit                        
       [Store operations that miss the first TLB level but hit the second and
        do not cause page walks]
  dtlb_store_misses.stlb_hit_2m                     
       [Store misses that miss the DTLB and hit the STLB (2M)]
  dtlb_store_misses.stlb_hit_4k                     
       [Store misses that miss the DTLB and hit the STLB (4K)]
  dtlb_store_misses.walk_completed                  
       [Store misses in all DTLB levels that cause completed page walks Spec
        update: BDM69]
  dtlb_store_misses.walk_completed_1g               
       [Store misses in all DTLB levels that cause completed page walks (1G)
        Spec update: BDM69]
  dtlb_store_misses.walk_completed_2m_4m            
       [Store misses in all DTLB levels that cause completed page walks
        (2M/4M) Spec update: BDM69]
  dtlb_store_misses.walk_completed_4k               
       [Store miss in all TLB levels causes a page walk that completes. (4K)
        Spec update: BDM69]
  dtlb_store_misses.walk_duration                   
       [Cycles when PMH is busy with page walks Spec update: BDM69]
  ept.walk_cycles                                   
       [Cycle count for an Extended Page table walk]
  itlb.itlb_flush                                   
       [Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages]
  itlb_misses.miss_causes_a_walk                    
       [Misses at all ITLB levels that cause page walks Spec update: BDM69]
  itlb_misses.stlb_hit                              
       [Operations that miss the first ITLB level but hit the second and do
        not cause any page walks]
  itlb_misses.stlb_hit_2m                           
       [Code misses that miss the DTLB and hit the STLB (2M)]
  itlb_misses.stlb_hit_4k                           
       [Core misses that miss the DTLB and hit the STLB (4K)]
  itlb_misses.walk_completed                        
       [Misses in all ITLB levels that cause completed page walks Spec update:
        BDM69]
  itlb_misses.walk_completed_1g                     
       [Store miss in all TLB levels causes a page walk that completes. (1G)
        Spec update: BDM69]
  itlb_misses.walk_completed_2m_4m                  
       [Code miss in all TLB levels causes a page walk that completes. (2M/4M)
        Spec update: BDM69]
  itlb_misses.walk_completed_4k                     
       [Code miss in all TLB levels causes a page walk that completes. (4K)
        Spec update: BDM69]
  itlb_misses.walk_duration                         
       [Cycles when PMH is busy with page walks Spec update: BDM69]
  page_walker_loads.dtlb_l1                         
       [Number of DTLB page walker hits in the L1+FB Spec update: BDM69, BDM98]
  page_walker_loads.dtlb_l2                         
       [Number of DTLB page walker hits in the L2 Spec update: BDM69, BDM98]
  page_walker_loads.dtlb_l3                         
       [Number of DTLB page walker hits in the L3 + XSNP Spec update: BDM69,
        BDM98]
  page_walker_loads.dtlb_memory                     
       [Number of DTLB page walker hits in Memory Spec update: BDM69, BDM98]
  page_walker_loads.itlb_l1                         
       [Number of ITLB page walker hits in the L1+FB Spec update: BDM69, BDM98]
  page_walker_loads.itlb_l2                         
       [Number of ITLB page walker hits in the L2 Spec update: BDM69, BDM98]
  page_walker_loads.itlb_l3                         
       [Number of ITLB page walker hits in the L3 + XSNP Spec update: BDM69,
        BDM98]
  tlb_flush.dtlb_thread                             
       [DTLB flush attempts of the thread-specific entries]
  tlb_flush.stlb_any                                
       [STLB flush attempts]
  rNNN                                               [Raw hardware event descriptor]
  cpu/t1=v1[,t2=v2,t3 ...]/modifier                  [Raw hardware event descriptor]
  mem:<addr>[/len][:access]                          [Hardware breakpoint]

Examine the output of the following in a terminal:

  • perf top
  • perf top -z
  • perf top -e cache-misses
  • perf top -e cache-misses,cycles
In [3]:
%%writefile tmp/transpose.c

#include <stdio.h>
#include <stdlib.h>
 
int main()
{
    const int m = 1024;
    const int n = 1024;
    int *matrix = malloc(sizeof(int) * m * n);
    int *transpose = malloc(sizeof(int) * m * n);
    
    for (int c = 0; c < m; c++)
       for(int d = 0; d < n; d++)
          matrix[c*m + d] = c+d;

    for (int i = 0; i < 300; ++i)
        for (int c = 0; c < m; c++)
           for(int d = 0 ; d < n ; d++)
              transpose[d*n + c] = matrix[c*m + d];
 
    printf("Transpose of the matrix:\n");
 
    int sum = 0;
    for (int c = 0; c < n; c++)
       for (int d = 0; d < m; d++)
          sum += transpose[d*n + c];
    printf("sum: %d\n", sum);

    return 0;
}
Overwriting tmp/transpose.c
In [4]:
!(cd tmp; gcc transpose.c -O3 -o transpose)
!bash -c "time ./tmp/transpose"
Transpose of the matrix:
sum: 1072693248

real	0m1.912s
user	0m1.909s
sys	0m0.000s
In [5]:
!perf record -e cycles,instructions ./tmp/transpose
Transpose of the matrix:
sum: 1072693248
[ perf record: Woken up 1 times to write data ]
[ perf record: Captured and wrote 0.742 MB perf.data (15234 samples) ]
  • Examine perf report in the terminal.
  • Now retry, this time building with -g instead of -O3
In [6]:
%%writefile tmp/matvec.py

import numpy as np

n = 4096
A = np.random.randn(n, n)
b = np.random.randn(n)

for i in range(10):
    A @ b
Overwriting tmp/matvec.py
In [7]:
!perf record python tmp/matvec.py
[ perf record: Woken up 1 times to write data ]
[ perf record: Captured and wrote 0.770 MB perf.data (19563 samples) ]
In [8]:
%%writefile tmp/matmat.py

import numpy as np

n = 2048
A = np.random.randn(n, n)
B = np.random.randn(n, n)

for i in range(10):
    A @ B
Overwriting tmp/matmat.py
In [9]:
!perf record python tmp/matmat.py
[ perf record: Woken up 1 times to write data ]
[ perf record: Captured and wrote 2.331 MB perf.data (60487 samples) ]

Run in shell separately:

perf record \
  -e cycles,L1-dcache-load-misses \
  -e fp_arith_inst_retired.256b_packed_double \
  -c 10 \
  python tmp/matvec.py
  • Also try -c 100

Look at:

  • perf help
  • perf help record

Aspects to mention:

  • Measuring parts of a program?
  • Granularity for ratios?
  • Scope of collection
  • Call graph collection (-g)
  • Precise events

Using pmu-tools / toplev

This uses toplev.py from Andi Kleen's pmu-tools.

  • Try the command below for a few different levels.
  • Try the command below for the matvec and the matmat.
In [28]:
%%bash

python2.7 ~/pack/pmu-tools/toplev.py -l3 python tmp/matvec.py
Using level 3.
perf stat -x\; --no-merge -e '{cpu/event=0x9c,umask=0x1/,cpu/event=0xc3,umask=0x1,edge=1,cmask=1/,cpu/event=0xc2,umask=0x2/,cpu/event=0xe,umask=0x1/,cycles,cpu/event=0x79,umask=0x30/,cpu/event=0x9c,umask=0x1,cmask=4/,cpu/event=0xc5,umask=0x0/,cpu/event=0xd,umask=0x3,cmask=1/,instructions},{cpu/event=0xb1,umask=0x1,cmask=2/,cpu/event=0xa2,umask=0x8/,cpu/event=0xb1,umask=0x1,cmask=1/,cpu/event=0xa3,umask=0x6,cmask=6/,cycles,cpu/event=0x9c,umask=0x1,cmask=4/,instructions,cpu/event=0xa3,umask=0x4,cmask=4/,cpu/event=0x5e,umask=0x1/,cpu/event=0xb1,umask=0x1,cmask=3/},{cpu/event=0x80,umask=0x4/,cpu/event=0xab,umask=0x2/,cpu/event=0xa2,umask=0x8/,cpu/event=0x14,umask=0x1/,cpu/event=0x87,umask=0x1/,cpu/event=0x79,umask=0x30,edge=1,cmask=1/,cpu/event=0xc1,umask=0x40/,cycles},{cpu/event=0xa8,umask=0x1,cmask=1/,cpu/event=0xa3,umask=0xc,cmask=12/,cpu/event=0x79,umask=0x24,cmask=4/,cpu/event=0xa3,umask=0x6,cmask=6/,cpu/event=0x79,umask=0x24,cmask=1/,cpu/event=0x79,umask=0x18,cmask=1/,cpu/event=0xa8,umask=0x1,cmask=4/,cycles,cpu/event=0x79,umask=0x18,cmask=4/},{cpu/event=0x85,umask=0x10,cmask=1/,cycles,cpu/event=0xc3,umask=0x1,edge=1,cmask=1/,cpu/event=0xa3,umask=0x5,cmask=5/,cpu/event=0x85,umask=0xe/,cpu/event=0x85,umask=0x60/,cpu/event=0xe6,umask=0x1f/,cpu/event=0xc5,umask=0x0/,cpu/event=0xa3,umask=0xc,cmask=12/},{cpu/event=0xa3,umask=0x5,cmask=5/,cpu/event=0xd1,umask=0x4/,cpu/event=0xd1,umask=0x20/,cycles},{cpu/event=0xc2,umask=0x2/,cpu/event=0xc7,umask=0x4/,cpu/event=0xc7,umask=0x10/,cpu/event=0xc7,umask=0x1/,cpu/event=0xc0,umask=0x2/,cpu/event=0xc7,umask=0x8/,cpu/event=0xc7,umask=0x20/,cpu/event=0xc7,umask=0x2/,instructions}' python tmp/matvec.py
# 3.4-full on Intel(R) Xeon(R) CPU E5-2650 v4 @ 2.20GHz
FE             Frontend_Bound.Frontend_Latency.MS_Switches:          4.76 +-     0.00 % Clocks
	This metric estimates the fraction of cycles when the CPU
	was stalled due to switches of uop delivery to the Microcode
	Sequencer (MS)...
	Sampling events:  idq.ms_switches
RET            Retiring.Microcode_Sequencer:                         5.94 +-     0.00 % Slots 
	This metric represents fraction of slots the CPU was
	retiring uops fetched by the Microcode Sequencer (MS) unit...
	Sampling events:  idq.ms_uops
BE             Backend_Bound:                                       42.79 +-     0.00 % Slots  <==
BE/Mem         Backend_Bound.Memory_Bound:                          21.05 +-     0.00 % Slots 
BE/Core        Backend_Bound.Core_Bound:                            21.74 +-     0.00 % Slots 
BE/Mem         Backend_Bound.Memory_Bound.L1_Bound:                 13.87 +-     0.00 % Stalls
	This metric estimates how often the CPU was stalled without
	loads missing the L1 data cache...
	Sampling events:  mem_load_uops_retired.l1_hit:pp mem_load_uops_retired.hit_lfb:pp
BE/Core        Backend_Bound.Core_Bound.Ports_Utilization:          26.25 +-     0.00 % Clocks
	This metric estimates fraction of cycles the CPU performance
	was potentially limited due to Core computation issues (non
	divider-related)...
               MUX:                                                 13.95 +-     0.00 %       
	PerfMon Event Multiplexing accuracy indicator

Using LIKWID

Uses pylikwid, a wrapper around likwid, which offers an analogous C API.

In [14]:
!likwid-perfctr -e
This architecture has 39 counters.
Counter tags(name, type<, options>):
BBOX0C1, Home Agent box 0, EDGEDETECT|THRESHOLD|INVERT
BBOX0C2, Home Agent box 0, EDGEDETECT|THRESHOLD|INVERT
BBOX0C3, Home Agent box 0, EDGEDETECT|THRESHOLD|INVERT
BBOX1C1, Home Agent box 1, EDGEDETECT|THRESHOLD|INVERT
BBOX1C2, Home Agent box 1, EDGEDETECT|THRESHOLD|INVERT
BBOX1C3, Home Agent box 1, EDGEDETECT|THRESHOLD|INVERT
MBOX2C1, Memory Controller 0 Channel 2, EDGEDETECT|THRESHOLD|INVERT
MBOX2C2, Memory Controller 0 Channel 2, EDGEDETECT|THRESHOLD|INVERT
MBOX2C3, Memory Controller 0 Channel 2, EDGEDETECT|THRESHOLD|INVERT
MBOX2FIX, Memory Controller 0 Channel 2 Fixed Counter, INVERT
MBOX3C1, Memory Controller 0 Channel 3, EDGEDETECT|THRESHOLD|INVERT
MBOX3C2, Memory Controller 0 Channel 3, EDGEDETECT|THRESHOLD|INVERT
MBOX3C3, Memory Controller 0 Channel 3, EDGEDETECT|THRESHOLD|INVERT
MBOX3FIX, Memory Controller 0 Channel 3 Fixed Counter, INVERT
MBOX6C1, Memory Controller 1 Channel 2, EDGEDETECT|THRESHOLD|INVERT
MBOX6C2, Memory Controller 1 Channel 2, EDGEDETECT|THRESHOLD|INVERT
MBOX6C3, Memory Controller 1 Channel 2, EDGEDETECT|THRESHOLD|INVERT
MBOX6FIX, Memory Controller 1 Channel 2 Fixed Counter, INVERT
MBOX7C1, Memory Controller 1 Channel 3, EDGEDETECT|THRESHOLD|INVERT
MBOX7C2, Memory Controller 1 Channel 3, EDGEDETECT|THRESHOLD|INVERT
MBOX7C3, Memory Controller 1 Channel 3, EDGEDETECT|THRESHOLD|INVERT
MBOX7FIX, Memory Controller 1 Channel 3 Fixed Counter, INVERT
PBOX1, Physical Layer box, EDGEDETECT|THRESHOLD|INVERT
PBOX2, Physical Layer box, EDGEDETECT|THRESHOLD|INVERT
PBOX3, Physical Layer box, EDGEDETECT|THRESHOLD|INVERT
RBOX0C1, Routing box 0, EDGEDETECT|THRESHOLD|INVERT
RBOX0C2, Routing box 0, EDGEDETECT|THRESHOLD|INVERT
RBOX1C1, Routing box 1, EDGEDETECT|THRESHOLD|INVERT
RBOX1C2, Routing box 1, EDGEDETECT|THRESHOLD|INVERT
QBOX0C1, QPI Link Layer 0, EDGEDETECT|THRESHOLD|INVERT
QBOX0C2, QPI Link Layer 0, EDGEDETECT|THRESHOLD|INVERT
QBOX0C3, QPI Link Layer 0, EDGEDETECT|THRESHOLD|INVERT
QBOX1C1, QPI Link Layer 1, EDGEDETECT|THRESHOLD|INVERT
QBOX1C2, QPI Link Layer 1, EDGEDETECT|THRESHOLD|INVERT
QBOX1C3, QPI Link Layer 1, EDGEDETECT|THRESHOLD|INVERT
QBOX0FIX1, QPI Link Layer rate status 0
QBOX0FIX2, QPI Link Layer rate status 0
QBOX1FIX1, QPI Link Layer rate status 1
QBOX1FIX2, QPI Link Layer rate status 1



This architecture has 1668 events.
Event tags (tag, id, umask, counters<, options>):
TEMP_CORE, 0x0, 0x0, TMP0
PWR_PKG_ENERGY, 0x2, 0x0, PWR0
PWR_PP0_ENERGY, 0x1, 0x0, PWR1
PWR_PP1_ENERGY, 0x4, 0x0, PWR2
PWR_DRAM_ENERGY, 0x3, 0x0, PWR3
INSTR_RETIRED_ANY, 0x0, 0x0, FIXC0
CPU_CLK_UNHALTED_CORE, 0x0, 0x0, FIXC1
CPU_CLK_UNHALTED_REF, 0x0, 0x0, FIXC2
LD_BLOCKS_STORE_FORWARD, 0x3, 0x2, PMC
LD_BLOCKS_NO_SR, 0x3, 0x8, PMC
MISALIGN_MEM_REF_LOADS, 0x5, 0x1, PMC
MISALIGN_MEM_REF_STORES, 0x5, 0x2, PMC
MISALIGN_MEM_REF_ANY, 0x5, 0x3, PMC
LD_BLOCKS_PARTIAL_ADDRESS_ALIAS, 0x7, 0x1, PMC
DTLB_LOAD_MISSES_CAUSES_A_WALK, 0x8, 0x1, PMC
DTLB_LOAD_MISSES_STLB_HIT, 0x8, 0x60, PMC
DTLB_LOAD_MISSES_WALK_COMPLETED, 0x8, 0xE, PMC
DTLB_LOAD_MISSES_STLB_HIT_4K, 0x8, 0x20, PMC
DTLB_LOAD_MISSES_WALK_COMPLETED_4K, 0x8, 0x2, PMC
DTLB_LOAD_MISSES_WALK_DURATION, 0x8, 0x10, PMC
INT_MISC_RECOVERY_CYCLES, 0xD, 0x3, PMC
INT_MISC_RECOVERY_COUNT, 0xD, 0x3, PMC
INT_MISC_RAT_STALL_CYCLES, 0xD, 0x8, PMC
INT_MISC_RAT_STALL_COUNT, 0xD, 0x8, PMC
UOPS_ISSUED_ANY, 0xE, 0x1, PMC
UOPS_ISSUED_FLAGS_MERGE, 0xE, 0x10, PMC
UOPS_ISSUED_SLOW_LEA, 0xE, 0x20, PMC
UOPS_ISSUED_SINGLE_MUL, 0xE, 0x40, PMC
UOPS_ISSUED_USED_CYCLES, 0xE, 0x1, PMC
UOPS_ISSUED_STALL_CYCLES, 0xE, 0x1, PMC
UOPS_ISSUED_TOTAL_CYCLES, 0xE, 0x1, PMC
UOPS_ISSUED_CORE_USED_CYCLES, 0xE, 0x1, PMC
UOPS_ISSUED_CORE_STALL_CYCLES, 0xE, 0x1, PMC
UOPS_ISSUED_CORE_TOTAL_CYCLES, 0xE, 0x1, PMC
UOPS_ISSUED_CYCLES_GE_1_UOPS_EXEC, 0xE, 0x1, PMC
UOPS_ISSUED_CYCLES_GE_2_UOPS_EXEC, 0xE, 0x1, PMC
UOPS_ISSUED_CYCLES_GE_3_UOPS_EXEC, 0xE, 0x1, PMC
UOPS_ISSUED_CYCLES_GE_4_UOPS_EXEC, 0xE, 0x1, PMC
UOPS_ISSUED_CYCLES_GE_5_UOPS_EXEC, 0xE, 0x1, PMC
UOPS_ISSUED_CYCLES_GE_6_UOPS_EXEC, 0xE, 0x1, PMC
ARITH_FPU_DIV_ACTIVE, 0x14, 0x1, PMC
L2_RQSTS_DEMAND_DATA_RD_MISS, 0x24, 0x21, PMC
L2_RQSTS_DEMAND_DATA_RD_HIT, 0x24, 0x41, PMC
L2_RQSTS_RFO_MISS, 0x24, 0x22, PMC
L2_RQSTS_RFO_HIT, 0x24, 0x42, PMC
L2_RQSTS_CODE_RD_MISS, 0x24, 0x24, PMC
L2_RQSTS_CODE_RD_HIT, 0x24, 0x44, PMC
L2_RQSTS_L2_PF_HIT, 0x24, 0x50, PMC
L2_RQSTS_L2_PF_MISS, 0x24, 0x30, PMC
L2_RQSTS_ALL_DEMAND_DATA_RD, 0x24, 0xE1, PMC
L2_RQSTS_ALL_DEMAND_MISS, 0x24, 0x27, PMC
L2_RQSTS_ALL_RFO, 0x24, 0xE2, PMC
L2_RQSTS_ALL_CODE_RD, 0x24, 0xE4, PMC
L2_RQSTS_ALL_DEMAND_REFERENCES, 0x24, 0xE7, PMC
L2_RQSTS_ALL_PF, 0x24, 0xF8, PMC
L2_RQSTS_MISS, 0x24, 0x3F, PMC
L2_RQSTS_REFERENCES, 0x24, 0xFF, PMC
L2_DEMAND_RQST_WB_HIT, 0x27, 0x50, PMC
LONGEST_LAT_CACHE_REFERENCE, 0x2E, 0x4F, PMC
LONGEST_LAT_CACHE_MISS, 0x2E, 0x41, PMC
CPU_CLOCK_UNHALTED_THREAD_P, 0x3C, 0x0, PMC
CPU_CLOCK_UNHALTED_REF_XCLK, 0x3C, 0x1, PMC
CPU_CLOCK_UNHALTED_ONE_THREAD_ACTIVE, 0x3C, 0x2, PMC
L1D_PEND_MISS_PENDING, 0x48, 0x1, PMC2
L1D_PEND_MISS_PENDING_CYCLES, 0x48, 0x1, PMC2
L1D_PEND_MISS_OCCURRENCES, 0x48, 0x1, PMC2
DTLB_STORE_MISSES_CAUSES_A_WALK, 0x49, 0x1, PMC
DTLB_STORE_MISSES_STLB_HIT, 0x49, 0x60, PMC
DTLB_STORE_MISSES_WALK_COMPLETED, 0x49, 0xE, PMC
DTLB_STORE_MISSES_STLB_HIT_4K, 0x49, 0x20, PMC
DTLB_STORE_MISSES_WALK_COMPLETED_4K, 0x49, 0x2, PMC
DTLB_STORE_MISSES_WALK_DURATION, 0x49, 0x10, PMC
LOAD_HIT_PRE_HW_PF, 0x4C, 0x2, PMC
EPT_WALK_CYCLES, 0x4F, 0x10, PMC
L1D_REPLACEMENT, 0x51, 0x1, PMC
L1D_M_EVICT, 0x51, 0x4, PMC
TX_MEM_ABORT_CONFLICT, 0x54, 0x1, PMC
TX_MEM_ABORT_CAPACITY_WRITE, 0x54, 0x2, PMC
TX_MEM_ABORT_HLE_STORE_TO_ELIDED_LOCK, 0x54, 0x4, PMC
TX_MEM_ABORT_HLE_ELISION_BUFFER_NOT_EMPTY, 0x54, 0x8, PMC
TX_MEM_ABORT_HLE_ELISION_BUFFER_MISMATCH, 0x54, 0x10, PMC
TX_MEM_ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT, 0x54, 0x20, PMC
TX_MEM_HLE_ELISION_BUFFER_FULL, 0x54, 0x40, PMC
MOVE_ELIMINATION_INT_NOT_ELIMINATED, 0x58, 0x4, PMC
MOVE_ELIMINATION_SIMD_NOT_ELIMINATED, 0x58, 0x8, PMC
MOVE_ELIMINATION_INT_ELIMINATED, 0x58, 0x1, PMC
MOVE_ELIMINATION_SIMD_ELIMINATED, 0x58, 0x2, PMC
CPL_CYCLES_RING0, 0x5C, 0x1, PMC
CPL_CYCLES_RING123, 0x5C, 0x2, PMC
CPL_CYCLES_RING0_TRANS, 0x5C, 0x1, PMC
RS_EVENTS_EMPTY_CYCLES, 0x5E, 0x1, PMC
OFFCORE_REQUESTS_OUTSTANDING_DEMAND_DATA_RD, 0x60, 0x1, PMC
OFFCORE_REQUESTS_OUTSTANDING_DEMAND_CODE_RD, 0x60, 0x2, PMC
OFFCORE_REQUESTS_OUTSTANDING_DEMAND_RFO, 0x60, 0x4, PMC
OFFCORE_REQUESTS_OUTSTANDING_ALL_DATA_RD, 0x60, 0x8, PMC
LOCK_CYCLES_SPLIT_LOCK_UC_LOCK_DURATION, 0x63, 0x1, PMC
LOCK_CYCLES_CACHE_LOCK_DURATION, 0x63, 0x2, PMC
IDQ_EMPTY, 0x79, 0x2, PMC
IDQ_MITE_UOPS, 0x79, 0x4, PMC
IDQ_DSB_UOPS, 0x79, 0x8, PMC
IDQ_MS_DSB_UOPS, 0x79, 0x10, PMC
IDQ_MS_MITE_UOPS, 0x79, 0x20, PMC
IDQ_MS_UOPS, 0x79, 0x30, PMC
IDQ_DSB_UOPS, 0x79, 0x18, PMC
IDQ_MITE_ALL_UOPS, 0x79, 0x24, PMC
IDQ_ALL_UOPS, 0x79, 0x3C, PMC
IDQ_MITE_CYCLES, 0x79, 0x4, PMC
IDQ_MITE_CYCLES_1_UOPS, 0x79, 0x4, PMC
IDQ_MITE_CYCLES_2_UOPS, 0x79, 0x4, PMC
IDQ_MITE_CYCLES_3_UOPS, 0x79, 0x4, PMC
IDQ_MITE_CYCLES_4_UOPS, 0x79, 0x4, PMC
IDQ_DSB_CYCLES, 0x79, 0x8, PMC
IDQ_DSB_CYCLES_1_UOPS, 0x79, 0x8, PMC
IDQ_DSB_CYCLES_2_UOPS, 0x79, 0x8, PMC
IDQ_DSB_CYCLES_3_UOPS, 0x79, 0x8, PMC
IDQ_DSB_CYCLES_4_UOPS, 0x79, 0x8, PMC
IDQ_MS_DSB_CYCLES, 0x79, 0x10, PMC
IDQ_MS_DSB_CYCLES_1_UOPS, 0x79, 0x10, PMC
IDQ_MS_DSB_CYCLES_2_UOPS, 0x79, 0x10, PMC
IDQ_MS_DSB_CYCLES_3_UOPS, 0x79, 0x10, PMC
IDQ_MS_DSB_CYCLES_4_UOPS, 0x79, 0x10, PMC
IDQ_MS_DSB_OCCUR, 0x79, 0x10, PMC
IDQ_MS_MITE_CYCLES, 0x79, 0x20, PMC
IDQ_MS_MITE_CYCLES_1_UOPS, 0x79, 0x20, PMC
IDQ_MS_MITE_CYCLES_2_UOPS, 0x79, 0x20, PMC
IDQ_MS_MITE_CYCLES_3_UOPS, 0x79, 0x20, PMC
IDQ_MS_MITE_CYCLES_4_UOPS, 0x79, 0x20, PMC
IDQ_MS_CYCLES, 0x79, 0x30, PMC
IDQ_MS_CYCLES_1_UOPS, 0x79, 0x30, PMC
IDQ_MS_CYCLES_2_UOPS, 0x79, 0x30, PMC
IDQ_MS_CYCLES_3_UOPS, 0x79, 0x30, PMC
IDQ_MS_CYCLES_4_UOPS, 0x79, 0x30, PMC
IDQ_MS_SWITCHES, 0x79, 0x30, PMC
IDQ_ALL_DSB_CYCLES_ANY_UOPS, 0x79, 0x18, PMC
IDQ_ALL_DSB_CYCLES_1_UOPS, 0x79, 0x18, PMC
IDQ_ALL_DSB_CYCLES_2_UOPS, 0x79, 0x18, PMC
IDQ_ALL_DSB_CYCLES_3_UOPS, 0x79, 0x18, PMC
IDQ_ALL_DSB_CYCLES_4_UOPS, 0x79, 0x18, PMC
IDQ_ALL_MITE_CYCLES_ANY_UOPS, 0x79, 0x24, PMC
IDQ_ALL_MITE_CYCLES_1_UOPS, 0x79, 0x24, PMC
IDQ_ALL_MITE_CYCLES_2_UOPS, 0x79, 0x24, PMC
IDQ_ALL_MITE_CYCLES_3_UOPS, 0x79, 0x24, PMC
IDQ_ALL_MITE_CYCLES_4_UOPS, 0x79, 0x24, PMC
IDQ_ALL_CYCLES_ANY_UOPS, 0x79, 0x3C, PMC
IDQ_ALL_CYCLES_1_UOPS, 0x79, 0x3C, PMC
IDQ_ALL_CYCLES_2_UOPS, 0x79, 0x3C, PMC
IDQ_ALL_CYCLES_3_UOPS, 0x79, 0x3C, PMC
IDQ_ALL_CYCLES_4_UOPS, 0x79, 0x3C, PMC
ICACHE_HIT, 0x80, 0x1, PMC
ICACHE_MISSES, 0x80, 0x2, PMC
ICACHE_ACCESSES, 0x80, 0x3, PMC
ITLB_MISSES_CAUSES_A_WALK, 0x85, 0x1, PMC
ITLB_MISSES_STLB_HIT, 0x85, 0x60, PMC
ITLB_MISSES_WALK_COMPLETED, 0x85, 0xE, PMC
ITLB_MISSES_STLB_HIT_4K, 0x85, 0x20, PMC
ITLB_MISSES_WALK_COMPLETED_4K, 0x85, 0x2, PMC
ITLB_MISSES_WALK_DURATION, 0x85, 0x10, PMC
ILD_STALL_LCP, 0x87, 0x1, PMC
BR_INST_EXEC_COND_TAKEN, 0x88, 0x81, PMC
BR_INST_EXEC_COND_NON_TAKEN, 0x88, 0x41, PMC
BR_INST_EXEC_DIRECT_JMP_TAKEN, 0x88, 0x82, PMC
BR_INST_EXEC_INDIRECT_JMP_NON_CALL_RET_TAKEN, 0x88, 0x84, PMC
BR_INST_EXEC_RETURN_NEAR_TAKEN, 0x88, 0x88, PMC
BR_INST_EXEC_DIRECT_NEAR_CALL_TAKEN, 0x88, 0x90, PMC
BR_INST_EXEC_INDIRECT_NEAR_CALL_TAKEN, 0x88, 0xA0, PMC
BR_INST_EXEC_ALL_CONDITIONAL, 0x88, 0xC1, PMC
BR_INST_EXEC_ALL_DIRECT_JMP, 0x88, 0xC2, PMC
BR_INST_EXEC_ALL_DIRECT_NEAR_CALL, 0x88, 0xD0, PMC
BR_INST_EXEC_ALL_INDIRECT_JUMP_NON_CALL_RET, 0x88, 0xC4, PMC
BR_INST_EXEC_ALL_INDIRECT_NEAR_RETURN, 0x88, 0xC8, PMC
BR_INST_EXEC_ALL_BRANCHES, 0x88, 0xFF, PMC
BR_MISP_EXEC_COND_TAKEN, 0x89, 0x81, PMC
BR_MISP_EXEC_COND_NON_TAKEN, 0x89, 0x41, PMC
BR_MISP_EXEC_INDIRECT_JMP_NON_CALL_RET_TAKEN, 0x89, 0x84, PMC
BR_MISP_EXEC_RETURN_NEAR_TAKEN, 0x89, 0x88, PMC
BR_MISP_EXEC_DIRECT_NEAR_CALL_TAKEN, 0x89, 0x90, PMC
BR_MISP_EXEC_INDIRECT_NEAR_CALL_TAKEN, 0x89, 0xA0, PMC
BR_MISP_EXEC_ALL_CONDITIONAL, 0x89, 0xC1, PMC
BR_MISP_EXEC_ALL_INDIRECT_JUMP_NON_CALL_RET, 0x89, 0xC4, PMC
BR_MISP_EXEC_ALL_BRANCHES, 0x89, 0xFF, PMC
IDQ_UOPS_NOT_DELIVERED_CORE, 0x9C, 0x1, PMC
IDQ_UOPS_NOT_DELIVERED_CYCLES_0_UOPS_DELIV_CORE, 0x9C, 0x1, PMC
IDQ_UOPS_NOT_DELIVERED_CYCLES_LE_1_UOP_DELIV_CORE, 0x9C, 0x1, PMC
IDQ_UOPS_NOT_DELIVERED_CYCLES_LE_2_UOP_DELIV_CORE, 0x9C, 0x1, PMC
IDQ_UOPS_NOT_DELIVERED_CYCLES_LE_3_UOP_DELIV_CORE, 0x9C, 0x1, PMC
IDQ_UOPS_NOT_DELIVERED_CYCLES_FE_WAS_OK, 0x9C, 0x1, PMC
UOP_DISPATCHES_CANCELLED_SIMD_PRF, 0xA0, 0x3, PMC
UOPS_EXECUTED_PORT_PORT_0, 0xA1, 0x1, PMC
UOPS_EXECUTED_PORT_PORT_1, 0xA1, 0x2, PMC
UOPS_EXECUTED_PORT_PORT_2, 0xA1, 0x4, PMC
UOPS_EXECUTED_PORT_PORT_3, 0xA1, 0x8, PMC
UOPS_EXECUTED_PORT_PORT_4, 0xA1, 0x10, PMC
UOPS_EXECUTED_PORT_PORT_5, 0xA1, 0x20, PMC
UOPS_EXECUTED_PORT_PORT_6, 0xA1, 0x40, PMC
UOPS_EXECUTED_PORT_PORT_7, 0xA1, 0x80, PMC
UOPS_EXECUTED_PORT_PORT_0_CORE, 0xA1, 0x1, PMC
UOPS_EXECUTED_PORT_PORT_1_CORE, 0xA1, 0x2, PMC
UOPS_EXECUTED_PORT_PORT_2_CORE, 0xA1, 0x4, PMC
UOPS_EXECUTED_PORT_PORT_3_CORE, 0xA1, 0x8, PMC
UOPS_EXECUTED_PORT_PORT_4_CORE, 0xA1, 0x10, PMC
UOPS_EXECUTED_PORT_PORT_5_CORE, 0xA1, 0x20, PMC
UOPS_EXECUTED_PORT_PORT_6_CORE, 0xA1, 0x40, PMC
UOPS_EXECUTED_PORT_PORT_7_CORE, 0xA1, 0x80, PMC
RESOURCE_STALLS_ANY, 0xA2, 0x1, PMC
RESOURCE_STALLS_RS, 0xA2, 0x4, PMC
RESOURCE_STALLS_SB, 0xA2, 0x8, PMC
RESOURCE_STALLS_ROB, 0xA2, 0x10, PMC
CYCLE_ACTIVITY_CYCLES_L1D_MISS, 0xA3, 0x8, PMC2
CYCLE_ACTIVITY_CYCLES_L2_MISS, 0xA3, 0x1, PMC
CYCLE_ACTIVITY_CYCLES_L2_PENDING, 0xA3, 0x1, PMC
CYCLE_ACTIVITY_CYCLES_MEM_ANY, 0xA3, 0x2, PMC
CYCLE_ACTIVITY_CYCLES_LDM_PENDING, 0xA3, 0x2, PMC
CYCLE_ACTIVITY_CYCLES_NO_EXECUTE, 0xA3, 0x4, PMC
CYCLE_ACTIVITY_STALLS_L1D_MISS, 0xA3, 0xC, PMC2
CYCLE_ACTIVITY_STALLS_L2_MISS, 0xA3, 0x5, PMC
CYCLE_ACTIVITY_STALLS_L2_PENDING, 0xA3, 0x5, PMC
CYCLE_ACTIVITY_STALLS_MEM_ANY, 0xA3, 0x6, PMC
CYCLE_ACTIVITY_STALLS_LDM_PENDING, 0xA3, 0x6, PMC
LSD_UOPS, 0xA8, 0x1, PMC
LSD_CYCLES_1_UOPS, 0xA8, 0x1, PMC
LSD_CYCLES_2_UOPS, 0xA8, 0x1, PMC
LSD_CYCLES_3_UOPS, 0xA8, 0x1, PMC
LSD_CYCLES_4_UOPS, 0xA8, 0x1, PMC
LSD_CYCLES_ACTIVE, 0xA8, 0x1, PMC
LSD_CYCLES_INACTIVE, 0xA8, 0x1, PMC
DSB2MITE_SWITCHES_PENALTY_CYCLES, 0xAB, 0x2, PMC
ITLB_ITLB_FLUSH, 0xAE, 0x1, PMC
OFFCORE_REQUESTS_DEMAND_DATA_RD, 0xB0, 0x1, PMC
OFFCORE_REQUESTS_DEMAND_CODE_RD, 0xB0, 0x2, PMC
OFFCORE_REQUESTS_DEMAND_RFO, 0xB0, 0x4, PMC
OFFCORE_REQUESTS_ALL_DATA_RD, 0xB0, 0x8, PMC
UOPS_EXECUTED_THREAD, 0xB1, 0x1, PMC
UOPS_EXECUTED_USED_CYCLES, 0xB1, 0x1, PMC
UOPS_EXECUTED_STALL_CYCLES, 0xB1, 0x1, PMC
UOPS_EXECUTED_TOTAL_CYCLES, 0xB1, 0x1, PMC
UOPS_EXECUTED_CYCLES_GE_1_UOPS_EXEC, 0xB1, 0x1, PMC
UOPS_EXECUTED_CYCLES_GE_2_UOPS_EXEC, 0xB1, 0x1, PMC
UOPS_EXECUTED_CYCLES_GE_3_UOPS_EXEC, 0xB1, 0x1, PMC
UOPS_EXECUTED_CYCLES_GE_4_UOPS_EXEC, 0xB1, 0x1, PMC
UOPS_EXECUTED_CYCLES_GE_5_UOPS_EXEC, 0xB1, 0x1, PMC
UOPS_EXECUTED_CYCLES_GE_6_UOPS_EXEC, 0xB1, 0x1, PMC
UOPS_EXECUTED_CYCLES_GE_7_UOPS_EXEC, 0xB1, 0x1, PMC
UOPS_EXECUTED_CYCLES_GE_8_UOPS_EXEC, 0xB1, 0x1, PMC
UOPS_EXECUTED_CORE, 0xB1, 0x2, PMC
UOPS_EXECUTED_CORE_USED_CYCLES, 0xB1, 0x2, PMC
UOPS_EXECUTED_CORE_STALL_CYCLES, 0xB1, 0x2, PMC
UOPS_EXECUTED_CORE_TOTAL_CYCLES, 0xB1, 0x2, PMC
UOPS_EXECUTED_CORE_CYCLES_GE_1_UOPS_EXEC, 0xB1, 0x2, PMC
UOPS_EXECUTED_CORE_CYCLES_GE_2_UOPS_EXEC, 0xB1, 0x2, PMC
UOPS_EXECUTED_CORE_CYCLES_GE_3_UOPS_EXEC, 0xB1, 0x2, PMC
UOPS_EXECUTED_CORE_CYCLES_GE_4_UOPS_EXEC, 0xB1, 0x2, PMC
UOPS_EXECUTED_CORE_CYCLES_GE_5_UOPS_EXEC, 0xB1, 0x2, PMC
UOPS_EXECUTED_CORE_CYCLES_GE_6_UOPS_EXEC, 0xB1, 0x2, PMC
UOPS_EXECUTED_CORE_CYCLES_GE_7_UOPS_EXEC, 0xB1, 0x2, PMC
UOPS_EXECUTED_CORE_CYCLES_GE_8_UOPS_EXEC, 0xB1, 0x2, PMC
OFFCORE_REQUESTS_BUFFER_SQ_FULL, 0xB2, 0x1, PMC
PAGE_WALKER_LOADS_DTLB_L1, 0xBC, 0x11, PMC
PAGE_WALKER_LOADS_ITLB_L1, 0xBC, 0x21, PMC
PAGE_WALKER_LOADS_DTLB_L2, 0xBC, 0x12, PMC
PAGE_WALKER_LOADS_ITLB_L2, 0xBC, 0x22, PMC
PAGE_WALKER_LOADS_DTLB_L3, 0xBC, 0x14, PMC
PAGE_WALKER_LOADS_ITLB_L3, 0xBC, 0x24, PMC
PAGE_WALKER_LOADS_DTLB_MEMORY, 0xBC, 0x18, PMC
INST_RETIRED_ANY_P, 0xC0, 0x0, PMC
INST_RETIRED_X87, 0xC0, 0x2, PMC
INST_RETIRED_PREC_DIST, 0xC0, 0x1, PMC1
OTHER_ASSISTS_AVX_TO_SSE, 0xC1, 0x8, PMC
OTHER_ASSISTS_SSE_TO_AVX, 0xC1, 0x10, PMC
OTHER_ASSISTS_ANY_WB_ASSIST, 0xC1, 0x40, PMC
UOPS_RETIRED_ALL, 0xC2, 0x1, PMC
UOPS_RETIRED_CORE_ALL, 0xC2, 0x1, PMC
UOPS_RETIRED_RETIRE_SLOTS, 0xC2, 0x2, PMC
UOPS_RETIRED_CORE_RETIRE_SLOTS, 0xC2, 0x2, PMC
UOPS_RETIRED_USED_CYCLES, 0xC2, 0x1, PMC
UOPS_RETIRED_STALL_CYCLES, 0xC2, 0x1, PMC
UOPS_RETIRED_TOTAL_CYCLES, 0xC2, 0x1, PMC
UOPS_RETIRED_CORE_ALL, 0xC2, 0x1, PMC
UOPS_RETIRED_CORE_RETIRE_SLOTS, 0xC2, 0x2, PMC
UOPS_RETIRED_CORE_USED_CYCLES, 0xC2, 0x1, PMC
UOPS_RETIRED_CORE_STALL_CYCLES, 0xC2, 0x1, PMC
UOPS_RETIRED_CORE_TOTAL_CYCLES, 0xC2, 0x1, PMC
UOPS_RETIRED_CYCLES_GE_1_UOPS_EXEC, 0xC2, 0x1, PMC
UOPS_RETIRED_CYCLES_GE_2_UOPS_EXEC, 0xC2, 0x1, PMC
UOPS_RETIRED_CYCLES_GE_3_UOPS_EXEC, 0xC2, 0x1, PMC
UOPS_RETIRED_CYCLES_GE_4_UOPS_EXEC, 0xC2, 0x1, PMC
UOPS_RETIRED_CYCLES_GE_5_UOPS_EXEC, 0xC2, 0x1, PMC
UOPS_RETIRED_CYCLES_GE_6_UOPS_EXEC, 0xC2, 0x1, PMC
UOPS_RETIRED_CYCLES_GE_7_UOPS_EXEC, 0xC2, 0x1, PMC
UOPS_RETIRED_CYCLES_GE_8_UOPS_EXEC, 0xC2, 0x1, PMC
MACHINE_CLEARS_COUNT, 0xC3, 0x1, PMC
MACHINE_CLEARS_CYCLES, 0xC3, 0x1, PMC
MACHINE_CLEARS_MEMORY_ORDERING, 0xC3, 0x2, PMC
MACHINE_CLEARS_SMC, 0xC3, 0x4, PMC
MACHINE_CLEARS_MASKMOV, 0xC3, 0x20, PMC
BR_INST_RETIRED_ALL_BRANCHES, 0xC4, 0x0, PMC
BR_INST_RETIRED_CONDITIONAL, 0xC4, 0x1, PMC
BR_INST_RETIRED_NEAR_CALL, 0xC4, 0x2, PMC
BR_INST_RETIRED_NEAR_RETURN, 0xC4, 0x8, PMC
BR_INST_RETIRED_NOT_TAKEN, 0xC4, 0x10, PMC
BR_INST_RETIRED_NEAR_TAKEN, 0xC4, 0x20, PMC
BR_INST_RETIRED_FAR_BRANCH, 0xC4, 0x40, PMC
BR_MISP_RETIRED_ALL_BRANCHES, 0xC5, 0x0, PMC
BR_MISP_RETIRED_CONDITIONAL, 0xC5, 0x1, PMC
BR_MISP_RETIRED_NEAR_TAKEN, 0xC5, 0x20, PMC
FP_ARITH_INST_RETIRED_SCALAR_DOUBLE, 0xC7, 0x1, PMC
FP_ARITH_INST_RETIRED_SCALAR_SINGLE, 0xC7, 0x2, PMC
FP_ARITH_INST_RETIRED_128B_PACKED_DOUBLE, 0xC7, 0x4, PMC
FP_ARITH_INST_RETIRED_128B_PACKED_SINGLE, 0xC7, 0x8, PMC
FP_ARITH_INST_RETIRED_256B_PACKED_DOUBLE, 0xC7, 0x10, PMC
FP_ARITH_INST_RETIRED_256B_PACKED_SINGLE, 0xC7, 0x20, PMC
FP_ARITH_INST_RETIRED_SCALAR, 0xC7, 0x3, PMC
FP_ARITH_INST_RETIRED_PACKED, 0xC7, 0x3C, PMC
FP_ARITH_INST_RETIRED_DOUBLE, 0xC7, 0x15, PMC
FP_ARITH_INST_RETIRED_SINGLE, 0xC7, 0x2A, PMC
HLE_RETIRED_START, 0xC8, 0x1, PMC
HLE_RETIRED_COMMIT, 0xC8, 0x2, PMC
HLE_RETIRED_ABORTED, 0xC8, 0x4, PMC
HLE_RETIRED_ABORTED_MISC1, 0xC8, 0x8, PMC
HLE_RETIRED_ABORTED_MISC2, 0xC8, 0x10, PMC
HLE_RETIRED_ABORTED_MISC3, 0xC8, 0x20, PMC
HLE_RETIRED_ABORTED_MISC4, 0xC8, 0x40, PMC
HLE_RETIRED_ABORTED_MISC5, 0xC8, 0x80, PMC
RTM_RETIRED_START, 0xC9, 0x1, PMC
RTM_RETIRED_COMMIT, 0xC9, 0x2, PMC
RTM_RETIRED_ABORTED, 0xC9, 0x4, PMC
RTM_RETIRED_ABORTED_MISC1, 0xC9, 0x8, PMC
RTM_RETIRED_ABORTED_MISC2, 0xC9, 0x10, PMC
RTM_RETIRED_ABORTED_MISC3, 0xC9, 0x20, PMC
RTM_RETIRED_ABORTED_MISC4, 0xC9, 0x40, PMC
RTM_RETIRED_ABORTED_MISC5, 0xC9, 0x80, PMC
FP_ASSIST_X87_OUTPUT, 0xCA, 0x2, PMC
FP_ASSIST_X87_INPUT, 0xCA, 0x4, PMC
FP_ASSIST_SIMD_OUTPUT, 0xCA, 0x8, PMC
FP_ASSIST_SIMD_INPUT, 0xCA, 0x10, PMC
FP_ASSIST_ANY, 0xCA, 0x1E, PMC
ROB_MISC_EVENT_LBR_INSERTS, 0xCC, 0x20, PMC
MEM_UOPS_RETIRED_LOADS_ALL, 0xD0, 0x81, PMC
MEM_UOPS_RETIRED_STORES_ALL, 0xD0, 0x82, PMC
MEM_UOPS_RETIRED_LOADS_LOCK, 0xD0, 0x21, PMC
MEM_UOPS_RETIRED_LOADS_STLB_MISS, 0xD0, 0x11, PMC
MEM_UOPS_RETIRED_STORES_STLB_MISS, 0xD0, 0x12, PMC
MEM_UOPS_RETIRED_LOADS_SPLIT, 0xD0, 0x41, PMC
MEM_UOPS_RETIRED_STORES_SPLIT, 0xD0, 0x42, PMC
MEM_LOAD_UOPS_RETIRED_L1_HIT, 0xD1, 0x1, PMC
MEM_LOAD_UOPS_RETIRED_L1_MISS, 0xD1, 0x8, PMC
MEM_LOAD_UOPS_RETIRED_L1_ALL, 0xD1, 0x9, PMC
MEM_LOAD_UOPS_RETIRED_L2_HIT, 0xD1, 0x2, PMC
MEM_LOAD_UOPS_RETIRED_L2_MISS, 0xD1, 0x10, PMC
MEM_LOAD_UOPS_RETIRED_L2_ALL, 0xD1, 0x12, PMC
MEM_LOAD_UOPS_RETIRED_L3_HIT, 0xD1, 0x4, PMC
MEM_LOAD_UOPS_RETIRED_L3_MISS, 0xD1, 0x20, PMC
MEM_LOAD_UOPS_RETIRED_L3_ALL, 0xD1, 0x24, PMC
MEM_LOAD_UOPS_RETIRED_HIT_LFB, 0xD1, 0x40, PMC
MEM_LOAD_UOPS_L3_HIT_RETIRED_XSNP_MISS, 0xD2, 0x1, PMC
MEM_LOAD_UOPS_L3_HIT_RETIRED_XSNP_HIT, 0xD2, 0x2, PMC
MEM_LOAD_UOPS_L3_HIT_RETIRED_XSNP_HITM, 0xD2, 0x4, PMC
MEM_LOAD_UOPS_L3_HIT_RETIRED_XSNP_NONE, 0xD2, 0x8, PMC
MEM_LOAD_UOPS_L3_MISS_RETIRED_LOCAL_DRAM, 0xD3, 0x1, PMC
MEM_LOAD_UOPS_L3_MISS_RETIRED_REMOTE_DRAM, 0xD3, 0x4, PMC
MEM_LOAD_UOPS_L3_MISS_RETIRED_REMOTE_HITM, 0xD3, 0x10, PMC
MEM_LOAD_UOPS_L3_MISS_RETIRED_REMOTE_FWD, 0xD3, 0x20, PMC
BACLEARS_ANY, 0xE6, 0x1F, PMC
L2_TRANS_DEMAND_DATA_RD, 0xF0, 0x1, PMC
L2_TRANS_RFO, 0xF0, 0x2, PMC
L2_TRANS_CODE_RD, 0xF0, 0x4, PMC
L2_TRANS_ALL_PF, 0xF0, 0x8, PMC
L2_TRANS_L1D_WB, 0xF0, 0x10, PMC
L2_TRANS_L2_FILL, 0xF0, 0x20, PMC
L2_TRANS_L2_WB, 0xF0, 0x40, PMC
L2_TRANS_ALL_REQUESTS, 0xF0, 0x80, PMC
L2_LINES_IN_I, 0xF1, 0x1, PMC
L2_LINES_IN_S, 0xF1, 0x2, PMC
L2_LINES_IN_E, 0xF1, 0x4, PMC
L2_LINES_IN_ALL, 0xF1, 0x7, PMC
L2_LINES_OUT_DEMAND_CLEAN, 0xF2, 0x5, PMC
L2_LINES_OUT_DEMAND_DIRTY, 0xF2, 0x6, PMC
OFFCORE_RESPONSE_0_OPTIONS, 0xB7, 0x1, PMC, MATCH0|MATCH1
OFFCORE_RESPONSE_0_DMND_DATA_RD_ANY, 0xB7, 0x1, PMC
OFFCORE_RESPONSE_0_DMND_RFO_ANY, 0xB7, 0x1, PMC
OFFCORE_RESPONSE_0_DMND_CODE_RD_ANY, 0xB7, 0x1, PMC
OFFCORE_RESPONSE_0_WB_ANY, 0xB7, 0x1, PMC
OFFCORE_RESPONSE_0_PF_L2_DATA_RD_ANY, 0xB7, 0x1, PMC
OFFCORE_RESPONSE_0_PF_L2_RFO_ANY, 0xB7, 0x1, PMC
OFFCORE_RESPONSE_0_PF_L2_CODE_RD_ANY, 0xB7, 0x1, PMC
OFFCORE_RESPONSE_0_PF_L3_DATA_RD_ANY, 0xB7, 0x1, PMC
OFFCORE_RESPONSE_0_PF_L3_RFO_ANY, 0xB7, 0x1, PMC
OFFCORE_RESPONSE_0_PF_L3_CODE_RD_ANY, 0xB7, 0x1, PMC
OFFCORE_RESPONSE_0_SPLIT_LOCK_UC_LOCK_ANY, 0xB7, 0x1, PMC
OFFCORE_RESPONSE_0_STREAMING_STORES_ANY, 0xB7, 0x1, PMC
OFFCORE_RESPONSE_0_OTHER_ANY, 0xB7, 0x1, PMC
OFFCORE_RESPONSE_1_OPTIONS, 0xBB, 0x1, PMC, MATCH0|MATCH1
OFFCORE_RESPONSE_1_DMND_DATA_RD_ANY, 0xBB, 0x1, PMC
OFFCORE_RESPONSE_1_DMND_RFO_ANY, 0xBB, 0x1, PMC
OFFCORE_RESPONSE_1_DMND_CODE_RD_ANY, 0xBB, 0x1, PMC
OFFCORE_RESPONSE_1_WB_ANY, 0xBB, 0x1, PMC
OFFCORE_RESPONSE_1_PF_L2_DATA_RD_ANY, 0xBB, 0x1, PMC
OFFCORE_RESPONSE_1_PF_L2_RFO_ANY, 0xBB, 0x1, PMC
OFFCORE_RESPONSE_1_PF_L2_CODE_RD_ANY, 0xBB, 0x1, PMC
OFFCORE_RESPONSE_1_PF_L3_DATA_RD_ANY, 0xBB, 0x1, PMC
OFFCORE_RESPONSE_1_PF_L3_RFO_ANY, 0xBB, 0x1, PMC
OFFCORE_RESPONSE_1_PF_L3_CODE_RD_ANY, 0xBB, 0x1, PMC
OFFCORE_RESPONSE_1_SPLIT_LOCK_UC_LOCK_ANY, 0xBB, 0x1, PMC
OFFCORE_RESPONSE_1_STREAMING_STORES_ANY, 0xBB, 0x1, PMC
OFFCORE_RESPONSE_1_OTHER_ANY, 0xBB, 0x1, PMC
EVENT_MSG_DOORBELL_RCVD, 0x42, 0x8, UBOX
PHOLD_CYCLES_ASSERT_TO_ACK, 0x45, 0x1, UBOX
RACU_REQUESTS, 0x46, 0x0, UBOX
UNCORE_CLOCK, 0x0, 0x0, UBOXFIX
CBOX_CLOCKTICKS, 0x0, 0x0, CBOX
TXR_INSERTS_AD_CACHE, 0x2, 0x1, CBOX
TXR_INSERTS_AK_CACHE, 0x2, 0x2, CBOX
TXR_INSERTS_BL_CACHE, 0x2, 0x4, CBOX
TXR_INSERTS_IV_CACHE, 0x2, 0x8, CBOX
TXR_INSERTS_AD_CORE, 0x2, 0x10, CBOX
TXR_INSERTS_AK_CORE, 0x2, 0x20, CBOX
TXR_INSERTS_BL_CORE, 0x2, 0x40, CBOX
TXR_ADS_USED_AD, 0x4, 0x1, CBOX
TXR_ADS_USED_AK, 0x4, 0x2, CBOX
TXR_ADS_USED_BL, 0x4, 0x4, CBOX
RING_BOUNCES_AD, 0x5, 0x1, CBOX
RING_BOUNCES_AK, 0x5, 0x2, CBOX
RING_BOUNCES_BL, 0x5, 0x4, CBOX
RING_BOUNCES_IV, 0x5, 0x10, CBOX
RING_SRC_THRTL, 0x7, 0x0, CBOX
FAST_ASSERTED, 0x9, 0x0, CBOX0C0|CBOX0C1|CBOX1C0|CBOX1C1|CBOX2C0|CBOX2C1|CBOX3C0|CBOX3C1|CBOX4C0|CBOX4C1|CBOX5C0|CBOX5C1|CBOX6C0|CBOX6C1|CBOX7C0|CBOX7C1|CBOX8C0|CBOX8C1|CBOX9C0|CBOX9C1|CBOX10C0|CBOX10C1|CBOX11C0|CBOX11C1|CBOX12C0|CBOX12C1|CBOX13C0|CBOX13C1|CBOX14C0|CBOX14C1|CBOX15C0|CBOX15C1|CBOX16C0|CBOX16C1|CBOX17C0|CBOX17C1|CBOX18C0|CBOX18C1|CBOX19C0|CBOX19C1|CBOX20C0|CBOX20C1|CBOX21C0|CBOX21C1|CBOX22C0|CBOX22C1|CBOX23C0|CBOX23C1
BOUNCE_CONTROL, 0xA, 0x0, CBOX
RING_AD_USED_UP_EVEN, 0x1B, 0x1, CBOX
RING_AD_USED_UP_ODD, 0x1B, 0x2, CBOX
RING_AD_USED_UP, 0x1B, 0x3, CBOX
RING_AD_USED_DOWN_EVEN, 0x1B, 0x4, CBOX
RING_AD_USED_DOWN_ODD, 0x1B, 0x8, CBOX
RING_AD_USED_DOWN, 0x1B, 0xC, CBOX
RING_AD_USED_ANY, 0x1B, 0xF, CBOX
RING_AK_USED_UP_EVEN, 0x1C, 0x1, CBOX
RING_AK_USED_UP_ODD, 0x1C, 0x2, CBOX
RING_AK_USED_UP, 0x1C, 0x3, CBOX
RING_AK_USED_DOWN_EVEN, 0x1C, 0x4, CBOX
RING_AK_USED_DOWN_ODD, 0x1C, 0x8, CBOX
RING_AK_USED_DOWN, 0x1C, 0xC, CBOX
RING_AK_USED_ANY, 0x1C, 0xF, CBOX
RING_BL_USED_UP_EVEN, 0x1D, 0x1, CBOX
RING_BL_USED_UP_ODD, 0x1D, 0x2, CBOX
RING_BL_USED_UP, 0x1D, 0x3, CBOX
RING_BL_USED_DOWN_EVEN, 0x1D, 0x4, CBOX
RING_BL_USED_DOWN_ODD, 0x1D, 0x8, CBOX
RING_BL_USED_DOWN, 0x1D, 0xC, CBOX
RING_BL_USED_ANY, 0x1D, 0xF, CBOX
RING_IV_USED_UP, 0x1E, 0x3, CBOX
RING_IV_USED_DN, 0x1E, 0xC, CBOX
RING_IV_USED_ANY, 0x1E, 0xF, CBOX
RING_IV_USED_DOWN, 0x1E, 0x33, CBOX
COUNTER0_OCCUPANCY, 0x1F, 0x0, CBOX
COUNTER0_OCCUPANCY_COUNT, 0x1F, 0x0, CBOX
RXR_OCCUPANCY_IRQ, 0x11, 0x1, CBOX0C0|CBOX1C0|CBOX2C0|CBOX3C0|CBOX4C0|CBOX5C0|CBOX6C0|CBOX7C0|CBOX8C0|CBOX9C0|CBOX10C0|CBOX11C0|CBOX12C0|CBOX13C0|CBOX14C0|CBOX15C0|CBOX16C0|CBOX17C0|CBOX18C0|CBOX19C0|CBOX20C0|CBOX21C0|CBOX22C0|CBOX23C0
RXR_OCCUPANCY_IRQ_REJ, 0x11, 0x2, CBOX0C0|CBOX1C0|CBOX2C0|CBOX3C0|CBOX4C0|CBOX5C0|CBOX6C0|CBOX7C0|CBOX8C0|CBOX9C0|CBOX10C0|CBOX11C0|CBOX12C0|CBOX13C0|CBOX14C0|CBOX15C0|CBOX16C0|CBOX17C0|CBOX18C0|CBOX19C0|CBOX20C0|CBOX21C0|CBOX22C0|CBOX23C0
RXR_OCCUPANCY_IPQ, 0x11, 0x4, CBOX0C0|CBOX1C0|CBOX2C0|CBOX3C0|CBOX4C0|CBOX5C0|CBOX6C0|CBOX7C0|CBOX8C0|CBOX9C0|CBOX10C0|CBOX11C0|CBOX12C0|CBOX13C0|CBOX14C0|CBOX15C0|CBOX16C0|CBOX17C0|CBOX18C0|CBOX19C0|CBOX20C0|CBOX21C0|CBOX22C0|CBOX23C0
RXR_OCCUPANCY_PRQ_REJ, 0x11, 0x20, CBOX0C0|CBOX1C0|CBOX2C0|CBOX3C0|CBOX4C0|CBOX5C0|CBOX6C0|CBOX7C0|CBOX8C0|CBOX9C0|CBOX10C0|CBOX11C0|CBOX12C0|CBOX13C0|CBOX14C0|CBOX15C0|CBOX16C0|CBOX17C0|CBOX18C0|CBOX19C0|CBOX20C0|CBOX21C0|CBOX22C0|CBOX23C0
RXR_EXT_STARVED_IRQ, 0x12, 0x1, CBOX
RXR_EXT_STARVED_IPQ, 0x12, 0x2, CBOX
RXR_EXT_STARVED_PRQ, 0x12, 0x4, CBOX
RXR_EXT_STARVED_ISMQ_BIDS, 0x12, 0x8, CBOX
RXR_INSERTS_IRQ, 0x13, 0x1, CBOX
RXR_INSERTS_IRQ_REJ, 0x13, 0x2, CBOX
RXR_INSERTS_IPQ, 0x13, 0x4, CBOX
RXR_INSERTS_PRQ, 0x13, 0x10, CBOX
RXR_INSERTS_PRQ_REJ, 0x13, 0x20, CBOX
RXR_IPQ_RETRY_ANY, 0x31, 0x1, CBOX
RXR_IPQ_RETRY_FULL, 0x31, 0x2, CBOX
RXR_IPQ_RETRY_ADDR_CONFLICT, 0x31, 0x4, CBOX
RXR_IPQ_RETRY_QPI_CREDITS, 0x31, 0x10, CBOX
RXR_IPQ_RETRY2_AD_SBO, 0x28, 0x1, CBOX
RXR_IPQ_RETRY2_TARGET, 0x28, 0x40, CBOX, NID
RXR_IRQ_RETRY_ANY, 0x32, 0x1, CBOX
RXR_IRQ_RETRY_FULL, 0x32, 0x2, CBOX
RXR_IRQ_RETRY_ADDR_CONFLICT, 0x32, 0x4, CBOX
RXR_IRQ_RETRY_RTID, 0x32, 0x8, CBOX
RXR_IRQ_RETRY_QPI_CREDITS, 0x32, 0x10, CBOX
RXR_IRQ_RETRY_IIO_CREDITS, 0x32, 0x20, CBOX
RXR_IRQ_RETRY_NID, 0x32, 0x40, CBOX, NID
RXR_IRQ_RETRY2_AD_SBO, 0x29, 0x1, CBOX
RXR_IRQ_RETRY2_BL_SBO, 0x29, 0x2, CBOX
RXR_IRQ_RETRY2_TARGET, 0x29, 0x40, CBOX, NID
RXR_ISMQ_RETRY_ANY, 0x33, 0x1, CBOX
RXR_ISMQ_RETRY_FULL, 0x33, 0x2, CBOX
RXR_ISMQ_RETRY_RTID, 0x33, 0x8, CBOX
RXR_ISMQ_RETRY_QPI_CREDITS, 0x33, 0x10, CBOX
RXR_ISMQ_RETRY_IIO_CREDITS, 0x33, 0x20, CBOX
RXR_ISMQ_RETRY_NID, 0x33, 0x40, CBOX, NID
RXR_ISMQ_RETRY_WB_CREDITS, 0x33, 0x80, CBOX, NID
RXR_ISMQ_RETRY2_AD_SBO, 0x2A, 0x1, CBOX
RXR_ISMQ_RETRY2_BL_SBO, 0x2A, 0x2, CBOX
RXR_ISMQ_RETRY2_TARGET, 0x2A, 0x40, CBOX, NID
LLC_LOOKUP_DATA_READ, 0x34, 0x3, CBOX, STATE
LLC_LOOKUP_WRITE, 0x34, 0x5, CBOX, STATE
LLC_LOOKUP_REMOTE_SNOOP, 0x34, 0x9, CBOX, STATE
LLC_LOOKUP_ANY, 0x34, 0x11, CBOX, STATE
LLC_LOOKUP_READ, 0x34, 0x21, CBOX, STATE
LLC_LOOKUP_NID, 0x34, 0x41, CBOX, NID|STATE
LLC_VICTIMS_M, 0x37, 0x1, CBOX
LLC_VICTIMS_E, 0x37, 0x2, CBOX
LLC_VICTIMS_S, 0x37, 0x4, CBOX
LLC_VICTIMS_F, 0x37, 0x8, CBOX
LLC_VICTIMS_MISS, 0x37, 0x10, CBOX
LLC_VICTIMS_NID, 0x37, 0x40, CBOX, NID|STATE
TOR_INSERTS_OPCODE, 0x35, 0x1, CBOX, OPCODE
TOR_INSERTS_MISS_OPCODE, 0x35, 0x3, CBOX, OPCODE
TOR_INSERTS_EVICTION, 0x35, 0x4, CBOX
TOR_INSERTS_ALL, 0x35, 0x8, CBOX
TOR_INSERTS_WB, 0x35, 0x10, CBOX
TOR_INSERTS_LOCAL_OPCODE, 0x35, 0x21, CBOX, OPCODE
TOR_INSERTS_MISS_LOCAL_OPCODE, 0x35, 0x23, CBOX, OPCODE
TOR_INSERTS_LOCAL, 0x35, 0x28, CBOX
TOR_INSERTS_MISS_LOCAL, 0x35, 0x2A, CBOX
TOR_INSERTS_NID_OPCODE, 0x35, 0x41, CBOX, OPCODE|NID
TOR_INSERTS_NID_MISS_OPCODE, 0x35, 0x43, CBOX, OPCODE|NID
TOR_INSERTS_NID_EVICION, 0x35, 0x44, CBOX, NID
TOR_INSERTS_NID_ALL, 0x35, 0x48, CBOX, NID
TOR_INSERTS_NID_MISS_ALL, 0x35, 0x4A, CBOX, NID
TOR_INSERTS_NID_WB, 0x35, 0x50, CBOX, NID
TOR_INSERTS_REMOTE_OPCODE, 0x35, 0x81, CBOX, OPCODE
TOR_INSERTS_MISS_REMOTE_OPCODE, 0x35, 0x83, CBOX, OPCODE
TOR_INSERTS_REMOTE, 0x35, 0x88, CBOX
TOR_INSERTS_MISS_REMOTE, 0x35, 0x8A, CBOX
TOR_OCCUPANCY_OPCODE, 0x36, 0x1, CBOX0C0|CBOX1C0|CBOX2C0|CBOX3C0|CBOX4C0|CBOX5C0|CBOX6C0|CBOX7C0|CBOX8C0|CBOX9C0|CBOX10C0|CBOX11C0|CBOX12C0|CBOX13C0|CBOX14C0|CBOX15C0|CBOX16C0|CBOX17C0|CBOX18C0|CBOX19C0|CBOX20C0|CBOX21C0|CBOX22C0|CBOX23C0, OPCODE
TOR_OCCUPANCY_MISS_OPCODE, 0x36, 0x3, CBOX0C0|CBOX1C0|CBOX2C0|CBOX3C0|CBOX4C0|CBOX5C0|CBOX6C0|CBOX7C0|CBOX8C0|CBOX9C0|CBOX10C0|CBOX11C0|CBOX12C0|CBOX13C0|CBOX14C0|CBOX15C0|CBOX16C0|CBOX17C0|CBOX18C0|CBOX19C0|CBOX20C0|CBOX21C0|CBOX22C0|CBOX23C0, OPCODE
TOR_OCCUPANCY_EVICTION, 0x36, 0x4, CBOX0C0|CBOX1C0|CBOX2C0|CBOX3C0|CBOX4C0|CBOX5C0|CBOX6C0|CBOX7C0|CBOX8C0|CBOX9C0|CBOX10C0|CBOX11C0|CBOX12C0|CBOX13C0|CBOX14C0|CBOX15C0|CBOX16C0|CBOX17C0|CBOX18C0|CBOX19C0|CBOX20C0|CBOX21C0|CBOX22C0|CBOX23C0
TOR_OCCUPANCY_ALL, 0x36, 0x8, CBOX0C0|CBOX1C0|CBOX2C0|CBOX3C0|CBOX4C0|CBOX5C0|CBOX6C0|CBOX7C0|CBOX8C0|CBOX9C0|CBOX10C0|CBOX11C0|CBOX12C0|CBOX13C0|CBOX14C0|CBOX15C0|CBOX16C0|CBOX17C0|CBOX18C0|CBOX19C0|CBOX20C0|CBOX21C0|CBOX22C0|CBOX23C0
TOR_OCCUPANCY_MISS_ALL, 0x36, 0xA, CBOX0C0|CBOX1C0|CBOX2C0|CBOX3C0|CBOX4C0|CBOX5C0|CBOX6C0|CBOX7C0|CBOX8C0|CBOX9C0|CBOX10C0|CBOX11C0|CBOX12C0|CBOX13C0|CBOX14C0|CBOX15C0|CBOX16C0|CBOX17C0|CBOX18C0|CBOX19C0|CBOX20C0|CBOX21C0|CBOX22C0|CBOX23C0
TOR_OCCUPANCY_WB, 0x36, 0x10, CBOX0C0|CBOX1C0|CBOX2C0|CBOX3C0|CBOX4C0|CBOX5C0|CBOX6C0|CBOX7C0|CBOX8C0|CBOX9C0|CBOX10C0|CBOX11C0|CBOX12C0|CBOX13C0|CBOX14C0|CBOX15C0|CBOX16C0|CBOX17C0|CBOX18C0|CBOX19C0|CBOX20C0|CBOX21C0|CBOX22C0|CBOX23C0
TOR_OCCUPANCY_LOCAL_OPCODE, 0x36, 0x21, CBOX0C0|CBOX1C0|CBOX2C0|CBOX3C0|CBOX4C0|CBOX5C0|CBOX6C0|CBOX7C0|CBOX8C0|CBOX9C0|CBOX10C0|CBOX11C0|CBOX12C0|CBOX13C0|CBOX14C0|CBOX15C0|CBOX16C0|CBOX17C0|CBOX18C0|CBOX19C0|CBOX20C0|CBOX21C0|CBOX22C0|CBOX23C0
TOR_OCCUPANCY_MISS_LOCAL_OPCODE, 0x36, 0x23, CBOX0C0|CBOX1C0|CBOX2C0|CBOX3C0|CBOX4C0|CBOX5C0|CBOX6C0|CBOX7C0|CBOX8C0|CBOX9C0|CBOX10C0|CBOX11C0|CBOX12C0|CBOX13C0|CBOX14C0|CBOX15C0|CBOX16C0|CBOX17C0|CBOX18C0|CBOX19C0|CBOX20C0|CBOX21C0|CBOX22C0|CBOX23C0
TOR_OCCUPANCY_LOCAL, 0x36, 0x28, CBOX0C0|CBOX1C0|CBOX2C0|CBOX3C0|CBOX4C0|CBOX5C0|CBOX6C0|CBOX7C0|CBOX8C0|CBOX9C0|CBOX10C0|CBOX11C0|CBOX12C0|CBOX13C0|CBOX14C0|CBOX15C0|CBOX16C0|CBOX17C0|CBOX18C0|CBOX19C0|CBOX20C0|CBOX21C0|CBOX22C0|CBOX23C0
TOR_OCCUPANCY_MISS_LOCAL, 0x36, 0x2A, CBOX0C0|CBOX1C0|CBOX2C0|CBOX3C0|CBOX4C0|CBOX5C0|CBOX6C0|CBOX7C0|CBOX8C0|CBOX9C0|CBOX10C0|CBOX11C0|CBOX12C0|CBOX13C0|CBOX14C0|CBOX15C0|CBOX16C0|CBOX17C0|CBOX18C0|CBOX19C0|CBOX20C0|CBOX21C0|CBOX22C0|CBOX23C0
TOR_OCCUPANCY_NID_OPCODE, 0x36, 0x41, CBOX0C0|CBOX1C0|CBOX2C0|CBOX3C0|CBOX4C0|CBOX5C0|CBOX6C0|CBOX7C0|CBOX8C0|CBOX9C0|CBOX10C0|CBOX11C0|CBOX12C0|CBOX13C0|CBOX14C0|CBOX15C0|CBOX16C0|CBOX17C0|CBOX18C0|CBOX19C0|CBOX20C0|CBOX21C0|CBOX22C0|CBOX23C0, OPCODE|NID
TOR_OCCUPANCY_NID_MISS_OPCODE, 0x36, 0x43, CBOX0C0|CBOX1C0|CBOX2C0|CBOX3C0|CBOX4C0|CBOX5C0|CBOX6C0|CBOX7C0|CBOX8C0|CBOX9C0|CBOX10C0|CBOX11C0|CBOX12C0|CBOX13C0|CBOX14C0|CBOX15C0|CBOX16C0|CBOX17C0|CBOX18C0|CBOX19C0|CBOX20C0|CBOX21C0|CBOX22C0|CBOX23C0, OPCODE|NID
TOR_OCCUPANCY_NID_EVICTION, 0x36, 0x44, CBOX0C0|CBOX1C0|CBOX2C0|CBOX3C0|CBOX4C0|CBOX5C0|CBOX6C0|CBOX7C0|CBOX8C0|CBOX9C0|CBOX10C0|CBOX11C0|CBOX12C0|CBOX13C0|CBOX14C0|CBOX15C0|CBOX16C0|CBOX17C0|CBOX18C0|CBOX19C0|CBOX20C0|CBOX21C0|CBOX22C0|CBOX23C0, NID
TOR_OCCUPANCY_NID_ALL, 0x36, 0x48, CBOX0C0|CBOX1C0|CBOX2C0|CBOX3C0|CBOX4C0|CBOX5C0|CBOX6C0|CBOX7C0|CBOX8C0|CBOX9C0|CBOX10C0|CBOX11C0|CBOX12C0|CBOX13C0|CBOX14C0|CBOX15C0|CBOX16C0|CBOX17C0|CBOX18C0|CBOX19C0|CBOX20C0|CBOX21C0|CBOX22C0|CBOX23C0, NID
TOR_OCCUPANCY_NID_MISS_ALL, 0x36, 0x4A, CBOX0C0|CBOX1C0|CBOX2C0|CBOX3C0|CBOX4C0|CBOX5C0|CBOX6C0|CBOX7C0|CBOX8C0|CBOX9C0|CBOX10C0|CBOX11C0|CBOX12C0|CBOX13C0|CBOX14C0|CBOX15C0|CBOX16C0|CBOX17C0|CBOX18C0|CBOX19C0|CBOX20C0|CBOX21C0|CBOX22C0|CBOX23C0, NID
TOR_OCCUPANCY_NID_WB, 0x36, 0x50, CBOX0C0|CBOX1C0|CBOX2C0|CBOX3C0|CBOX4C0|CBOX5C0|CBOX6C0|CBOX7C0|CBOX8C0|CBOX9C0|CBOX10C0|CBOX11C0|CBOX12C0|CBOX13C0|CBOX14C0|CBOX15C0|CBOX16C0|CBOX17C0|CBOX18C0|CBOX19C0|CBOX20C0|CBOX21C0|CBOX22C0|CBOX23C0, NID
TOR_OCCUPANCY_REMOTE_OPCODE, 0x36, 0x81, CBOX0C0|CBOX1C0|CBOX2C0|CBOX3C0|CBOX4C0|CBOX5C0|CBOX6C0|CBOX7C0|CBOX8C0|CBOX9C0|CBOX10C0|CBOX11C0|CBOX12C0|CBOX13C0|CBOX14C0|CBOX15C0|CBOX16C0|CBOX17C0|CBOX18C0|CBOX19C0|CBOX20C0|CBOX21C0|CBOX22C0|CBOX23C0, OPCODE
TOR_OCCUPANCY_MISS_REMOTE_OPCODE, 0x36, 0x83, CBOX0C0|CBOX1C0|CBOX2C0|CBOX3C0|CBOX4C0|CBOX5C0|CBOX6C0|CBOX7C0|CBOX8C0|CBOX9C0|CBOX10C0|CBOX11C0|CBOX12C0|CBOX13C0|CBOX14C0|CBOX15C0|CBOX16C0|CBOX17C0|CBOX18C0|CBOX19C0|CBOX20C0|CBOX21C0|CBOX22C0|CBOX23C0, OPCODE
TOR_OCCUPANCY_REMOTE, 0x36, 0x88, CBOX0C0|CBOX1C0|CBOX2C0|CBOX3C0|CBOX4C0|CBOX5C0|CBOX6C0|CBOX7C0|CBOX8C0|CBOX9C0|CBOX10C0|CBOX11C0|CBOX12C0|CBOX13C0|CBOX14C0|CBOX15C0|CBOX16C0|CBOX17C0|CBOX18C0|CBOX19C0|CBOX20C0|CBOX21C0|CBOX22C0|CBOX23C0
TOR_OCCUPANCY_MISS_REMOTE, 0x36, 0x8A, CBOX0C0|CBOX1C0|CBOX2C0|CBOX3C0|CBOX4C0|CBOX5C0|CBOX6C0|CBOX7C0|CBOX8C0|CBOX9C0|CBOX10C0|CBOX11C0|CBOX12C0|CBOX13C0|CBOX14C0|CBOX15C0|CBOX16C0|CBOX17C0|CBOX18C0|CBOX19C0|CBOX20C0|CBOX21C0|CBOX22C0|CBOX23C0
MISC_RSPI_WAS_FSE, 0x39, 0x1, CBOX
MISC_WC_ALIASING, 0x39, 0x2, CBOX
MISC_STARTED, 0x39, 0x4, CBOX
MISC_RFO_HIT_S, 0x39, 0x8, CBOX
MISC_CVZERO_PREFETCH_VICTIM, 0x39, 0x10, CBOX
MISC_CVZERO_PREFETCH_MISS, 0x39, 0x20, CBOX
SBO_CREDITS_ACQUIRED_AD, 0x3D, 0x1, CBOX
SBO_CREDITS_ACQUIRED_BL, 0x3D, 0x2, CBOX
SBO_CREDITS_ACQUIRED_ANY, 0x3D, 0x3, CBOX
SBO_CREDIT_OCCUPANCY_AD, 0x3E, 0x1, CBOX
SBO_CREDIT_OCCUPANCY_BL, 0x3E, 0x2, CBOX
SBO_CREDIT_OCCUPANCY_ANY, 0x3E, 0x3, CBOX
WBOX_CLOCKTICKS, 0x0, 0x0, WBOX
CORE0_TRANSITION_CYCLES, 0x60, 0x0, WBOX
CORE1_TRANSITION_CYCLES, 0x61, 0x0, WBOX
CORE2_TRANSITION_CYCLES, 0x62, 0x0, WBOX
CORE3_TRANSITION_CYCLES, 0x63, 0x0, WBOX
CORE4_TRANSITION_CYCLES, 0x64, 0x0, WBOX
CORE5_TRANSITION_CYCLES, 0x65, 0x0, WBOX
CORE6_TRANSITION_CYCLES, 0x66, 0x0, WBOX
CORE7_TRANSITION_CYCLES, 0x67, 0x0, WBOX
CORE8_TRANSITION_CYCLES, 0x68, 0x0, WBOX
CORE9_TRANSITION_CYCLES, 0x69, 0x0, WBOX
CORE10_TRANSITION_CYCLES, 0x6A, 0x0, WBOX
CORE11_TRANSITION_CYCLES, 0x6B, 0x0, WBOX
CORE12_TRANSITION_CYCLES, 0x6C, 0x0, WBOX
CORE13_TRANSITION_CYCLES, 0x6D, 0x0, WBOX
CORE14_TRANSITION_CYCLES, 0x6E, 0x0, WBOX
CORE15_TRANSITION_CYCLES, 0x6F, 0x0, WBOX
CORE16_TRANSITION_CYCLES, 0x70, 0x0, WBOX
CORE17_TRANSITION_CYCLES, 0x71, 0x0, WBOX
FIVR_PS_PS0_CYCLES, 0x75, 0x0, WBOX
FIVR_PS_PS1_CYCLES, 0x75, 0x0, WBOX
FIVR_PS_PS2_CYCLES, 0x75, 0x0, WBOX
FIVR_PS_PS3_CYCLES, 0x75, 0x0, WBOX
DEMOTIONS_CORE0, 0x30, 0x0, WBOX
DEMOTIONS_CORE1, 0x31, 0x0, WBOX
DEMOTIONS_CORE2, 0x32, 0x0, WBOX
DEMOTIONS_CORE3, 0x33, 0x0, WBOX
DEMOTIONS_CORE4, 0x34, 0x0, WBOX
DEMOTIONS_CORE5, 0x35, 0x0, WBOX
DEMOTIONS_CORE6, 0x36, 0x0, WBOX
DEMOTIONS_CORE7, 0x37, 0x0, WBOX
DEMOTIONS_CORE8, 0x38, 0x0, WBOX
DEMOTIONS_CORE9, 0x39, 0x0, WBOX
DEMOTIONS_CORE10, 0x3A, 0x0, WBOX
DEMOTIONS_CORE11, 0x3B, 0x0, WBOX
DEMOTIONS_CORE12, 0x3C, 0x0, WBOX
DEMOTIONS_CORE13, 0x3D, 0x0, WBOX
DEMOTIONS_CORE14, 0x3E, 0x0, WBOX
DEMOTIONS_CORE15, 0x3F, 0x0, WBOX
DEMOTIONS_CORE16, 0x40, 0x0, WBOX
DEMOTIONS_CORE17, 0x41, 0x0, WBOX
FREQ_BAND0_CYCLES, 0xB, 0x0, WBOX, OCCUPANCY_FILTER
FREQ_BAND1_CYCLES, 0xC, 0x0, WBOX, OCCUPANCY_FILTER
FREQ_BAND2_CYCLES, 0xD, 0x0, WBOX, OCCUPANCY_FILTER
FREQ_BAND3_CYCLES, 0xE, 0x0, WBOX, OCCUPANCY_FILTER
FREQ_MAX_LIMIT_THERMAL_CYCLES, 0x4, 0x0, WBOX
FREQ_MAX_OS_CYCLES, 0x6, 0x0, WBOX
FREQ_MAX_POWER_CYCLES, 0x5, 0x0, WBOX
FREQ_MIN_IO_P_CYCLES, 0x73, 0x0, WBOX
FREQ_TRANS_CYCLES, 0x74, 0x0, WBOX
MEMORY_PHASE_SHEDDING_CYCLES, 0x2F, 0x0, WBOX
POWER_STATE_OCCUPANCY_CORES_C0, 0x80, 0x40, WBOX
POWER_STATE_OCCUPANCY_CORES_C3, 0x80, 0x80, WBOX
POWER_STATE_OCCUPANCY_CORES_C6, 0x80, 0xC0, WBOX
PROCHOT_EXTERNAL_CYCLES, 0xA, 0x0, WBOX
PROCHOT_INTERNAL_CYCLES, 0x9, 0x0, WBOX
TOTAL_TRANSITION_CYCLES, 0x72, 0x0, WBOX
VR_HOT_CYCLES, 0x42, 0x0, WBOX
UFS_BANDWIDTH_MAX_RANGE, 0x7E, 0x0, WBOX
UFS_TRANSITIONS_DOWN, 0x7C, 0x0, WBOX
UFS_TRANSITIONS_IO_P_LIMIT, 0x7D, 0x0, WBOX
UFS_TRANSITIONS_NO_CHANGE, 0x79, 0x0, WBOX
UFS_TRANSITIONS_UP_RING, 0x7A, 0x0, WBOX
UFS_TRANSITIONS_UP_STALL, 0x7B, 0x0, WBOX
CORES_IN_C3, 0x0, 0x0, WBOX0FIX
CORES_IN_C6, 0x0, 0x0, WBOX1FIX
BBOX_CLOCKTICKS, 0x0, 0x0, BBOX
ADDR_OPC_MATCH_ADDR, 0x20, 0x1, BBOX, MATCH0|MATCH1
ADDR_OPC_MATCH_OPC, 0x20, 0x2, BBOX, OPCODE
ADDR_OPC_MATCH_FILT, 0x20, 0x3, BBOX, OPCODE|MATCH0|MATCH1
ADDR_OPC_MATCH_AD, 0x20, 0x4, BBOX, OPCODE
ADDR_OPC_MATCH_BL, 0x20, 0x8, BBOX, OPCODE
ADDR_OPC_MATCH_AK, 0x20, 0x10, BBOX, OPCODE
BT_CYCLES_NE, 0x42, 0x0, BBOX
BT_OCCUPANCY, 0x43, 0x0, BBOX
BYPASS_IMC_TAKEN, 0x14, 0x1, BBOX
BYPASS_IMC_NOT_TAKEN, 0x14, 0x2, BBOX
CONFLICT_CYCLES, 0xB, 0x0, BBOX0C1|BBOX1C1
DIRECT2CORE_COUNT, 0x11, 0x0, BBOX
DIRECT2CORE_CYCLES_DISABLED, 0x12, 0x0, BBOX
DIRECT2CORE_TXN_OVERRIDE, 0x13, 0x0, BBOX
DIRECTORY_LAT_OPT, 0x41, 0x0, BBOX
DIRECTORY_LOOKUP_SNP, 0xC, 0x1, BBOX
DIRECTORY_LOOKUP_NO_SNP, 0xC, 0x2, BBOX
DIRECTORY_UPDATE_SET, 0xD, 0x1, BBOX
DIRECTORY_UPDATE_CLEAR, 0xD, 0x2, BBOX
DIRECTORY_UPDATE_ANY, 0xD, 0x3, BBOX
HITME_LOOKUP_READ_OR_INVITOE, 0x70, 0x1, BBOX
HITME_LOOKUP_WBMTOI, 0x70, 0x2, BBOX
HITME_LOOKUP_ACKCNFLTWBI, 0x70, 0x4, BBOX
HITME_LOOKUP_WBMTOE_OR_S, 0x70, 0x8, BBOX
HITME_LOOKUP_HOM, 0x70, 0xF, BBOX
HITME_LOOKUP_RSPFWDI_REMOTE, 0x70, 0x10, BBOX
HITME_LOOKUP_RSPFWDI_LOCAL, 0x70, 0x20, BBOX
HITME_LOOKUP_INVALS, 0x70, 0x26, BBOX
HITME_LOOKUP_RSPFWDS, 0x70, 0x40, BBOX
HITME_LOOKUP_ALLOCS, 0x70, 0x70, BBOX
HITME_LOOKUP_RSP, 0x70, 0x80, BBOX
HITME_LOOKUP_ALL, 0x70, 0xFF, BBOX
HITME_HIT_READ_OR_INVITOE, 0x71, 0x1, BBOX
HITME_HIT_WBMTOI, 0x71, 0x2, BBOX
HITME_HIT_ACKCNFLTWBI, 0x71, 0x4, BBOX
HITME_HIT_WBMTOE_OR_S, 0x71, 0x8, BBOX
HITME_HIT_HOM, 0x71, 0xF, BBOX
HITME_HIT_RSPFWDI_REMOTE, 0x71, 0x10, BBOX
HITME_HIT_RSPFWDI_LOCAL, 0x71, 0x20, BBOX
HITME_HIT_INVALS, 0x71, 0x26, BBOX
HITME_HIT_RSPFWDS, 0x71, 0x40, BBOX
HITME_HIT_EVICTS, 0x71, 0x42, BBOX
HITME_HIT_ALLOCS, 0x71, 0x70, BBOX
HITME_HIT_RSP, 0x71, 0x80, BBOX
HITME_HIT_ALL, 0x71, 0xFF, BBOX
HITME_HIT_PV_BITS_SET_READ_OR_INVITOE, 0x72, 0x1, BBOX
HITME_HIT_PV_BITS_SET_WBMTOI, 0x72, 0x2, BBOX
HITME_HIT_PV_BITS_SET_ACKCNFLTWBI, 0x72, 0x4, BBOX
HITME_HIT_PV_BITS_SET_WBMTOE_OR_S, 0x72, 0x8, BBOX
HITME_HIT_PV_BITS_SET_HOM, 0x72, 0xF, BBOX
HITME_HIT_PV_BITS_SET_RSPFWDI_REMOTE, 0x72, 0x10, BBOX
HITME_HIT_PV_BITS_SET_RSPFWDI_LOCAL, 0x72, 0x20, BBOX
HITME_HIT_PV_BITS_SET_RSPFWDS, 0x72, 0x40, BBOX
HITME_HIT_PV_BITS_SET_RSP, 0x72, 0x80, BBOX
HITME_HIT_PV_BITS_SET_ALL, 0x72, 0xFF, BBOX
IGR_NO_CREDIT_CYCLES_AD_QPI0, 0x22, 0x1, BBOX
IGR_NO_CREDIT_CYCLES_AD_QPI1, 0x22, 0x2, BBOX
IGR_NO_CREDIT_CYCLES_AD_QPI2, 0x22, 0x10, BBOX
IGR_NO_CREDIT_CYCLES_BL_QPI0, 0x22, 0x4, BBOX
IGR_NO_CREDIT_CYCLES_BL_QPI1, 0x22, 0x8, BBOX
IGR_NO_CREDIT_CYCLES_BL_QPI2, 0x22, 0x20, BBOX
IMC_READS_NORMAL, 0x17, 0x1, BBOX
IMC_RETRY, 0x1E, 0x0, BBOX
IMC_WRITES_FULL, 0x1A, 0x1, BBOX
IMC_WRITES_PARTIAL, 0x1A, 0x2, BBOX
IMC_WRITES_FULL_ISOCH, 0x1A, 0x4, BBOX
IMC_WRITES_PARTIAL_ISOCH, 0x1A, 0x8, BBOX
IMC_WRITES_ALL, 0x1A, 0xF, BBOX
OSB_READS_LOCAL, 0x53, 0x2, BBOX
OSB_INVITOE_LOCAL, 0x53, 0x4, BBOX
OSB_REMOTE, 0x53, 0x8, BBOX
OSB_CANCELLED, 0x53, 0x10, BBOX
OSB_READS_LOCAL_USEFUL, 0x53, 0x20, BBOX
OSB_REMOTE_USEFUL, 0x53, 0x40, BBOX
OSB_EDR_ALL, 0x54, 0x1, BBOX
OSB_EDR_READS_LOCAL_I, 0x54, 0x2, BBOX
OSB_EDR_READS_REMOTE_I, 0x54, 0x4, BBOX
OSB_EDR_READS_LOCAL_S, 0x54, 0x8, BBOX
OSB_EDR_READS_REMOTE_S, 0x54, 0x10, BBOX
REQUESTS_READS_LOCAL, 0x1, 0x1, BBOX
REQUESTS_READS_REMOTE, 0x1, 0x2, BBOX
REQUESTS_READS, 0x1, 0x3, BBOX
REQUESTS_WRITES_LOCAL, 0x1, 0x4, BBOX
REQUESTS_WRITES_REMOTE, 0x1, 0x8, BBOX
REQUESTS_WRITES, 0x1, 0xC, BBOX
REQUESTS_INVITOE_LOCAL, 0x1, 0x10, BBOX
REQUESTS_INVITOE_REMOTE, 0x1, 0x20, BBOX
REQUESTS_ALL_LOCAL, 0x1, 0x15, BBOX
REQUESTS_ALL_REMOTE, 0x1, 0x2A, BBOX
REQUESTS_ALL, 0x1, 0x3F, BBOX
RING_AD_USED_CW_EVEN, 0x3E, 0x1, BBOX
RING_AD_USED_CW_ODD, 0x3E, 0x2, BBOX
RING_AD_USED_CW, 0x3E, 0x3, BBOX
RING_AD_USED_CCW_EVEN, 0x3E, 0x4, BBOX
RING_AD_USED_CCW_ODD, 0x3E, 0x8, BBOX
RING_AD_USED_CCW, 0x3E, 0xC, BBOX
RING_AK_USED_CW_EVEN, 0x3F, 0x1, BBOX
RING_AK_USED_CW_ODD, 0x3F, 0x2, BBOX
RING_AK_USED_CW, 0x3F, 0x3, BBOX
RING_AK_USED_CCW_EVEN, 0x3F, 0x4, BBOX
RING_AK_USED_CCW_ODD, 0x3F, 0x8, BBOX
RING_AK_USED_CCW, 0x3F, 0xC, BBOX
RING_BL_USED_CW_EVEN, 0x40, 0x1, BBOX
RING_BL_USED_CW_ODD, 0x40, 0x2, BBOX
RING_BL_USED_CW, 0x40, 0x3, BBOX
RING_BL_USED_CCW_EVEN, 0x40, 0x4, BBOX
RING_BL_USED_CCW_ODD, 0x40, 0x8, BBOX
RING_BL_USED_CCW, 0x40, 0xC, BBOX
RPQ_CYCLES_NO_REG_CREDITS_CHN0, 0x15, 0x1, BBOX
RPQ_CYCLES_NO_REG_CREDITS_CHN1, 0x15, 0x2, BBOX
RPQ_CYCLES_NO_REG_CREDITS_CHN2, 0x15, 0x4, BBOX
RPQ_CYCLES_NO_REG_CREDITS_CHN3, 0x15, 0x8, BBOX
RPQ_CYCLES_NO_REG_CREDITS_ALL, 0x15, 0xF, BBOX
WPQ_CYCLES_NO_REG_CREDITS_CHN0, 0x18, 0x1, BBOX
WPQ_CYCLES_NO_REG_CREDITS_CHN1, 0x18, 0x2, BBOX
WPQ_CYCLES_NO_REG_CREDITS_CHN2, 0x18, 0x4, BBOX
WPQ_CYCLES_NO_REG_CREDITS_CHN3, 0x18, 0x8, BBOX
WPQ_CYCLES_NO_REG_CREDITS_ALL, 0x18, 0xF, BBOX
SBO0_CREDITS_ACQUIRED_AD, 0x68, 0x1, BBOX
SBO0_CREDITS_ACQUIRED_BL, 0x68, 0x2, BBOX
SBO0_CREDIT_OCCUPANCY_AD, 0x6A, 0x1, BBOX
SBO0_CREDIT_OCCUPANCY_BL, 0x6A, 0x2, BBOX
SBO1_CREDITS_ACQUIRED_AD, 0x69, 0x1, BBOX
SBO1_CREDITS_ACQUIRED_BL, 0x69, 0x2, BBOX
SBO1_CREDIT_OCCUPANCY_AD, 0x6B, 0x1, BBOX
SBO1_CREDIT_OCCUPANCY_BL, 0x6B, 0x2, BBOX
SNOOPS_RSP_AFTER_DATA_LOCAL, 0xA, 0x1, BBOX
SNOOPS_RSP_AFTER_DATA_REMOTE, 0xA, 0x2, BBOX
SNOOP_CYCLES_NE_LOCAL, 0x8, 0x1, BBOX
SNOOP_CYCLES_NE_REMOTE, 0x8, 0x2, BBOX
SNOOP_CYCLES_NE_ALL, 0x8, 0x3, BBOX
SNOOP_OCCUPANCY_LOCAL, 0x9, 0x1, BBOX
SNOOP_OCCUPANCY_REMOTE, 0x9, 0x2, BBOX
SNOOP_RESP_RSPI, 0x21, 0x1, BBOX
SNOOP_RESP_RSPS, 0x21, 0x2, BBOX
SNOOP_RESP_RSPIFWD, 0x21, 0x4, BBOX
SNOOP_RESP_RSPSFWD, 0x21, 0x8, BBOX
SNOOP_RESP_RSP_WB, 0x21, 0x10, BBOX
SNOOP_RESP_RSP_FWD_WB, 0x21, 0x20, BBOX
SNOOP_RESP_RSPCNFLCT, 0x21, 0x40, BBOX
SNP_RESP_RECV_LOCAL_RSPI, 0x60, 0x1, BBOX
SNP_RESP_RECV_LOCAL_RSPS, 0x60, 0x2, BBOX
SNP_RESP_RECV_LOCAL_RSPIFWD, 0x60, 0x4, BBOX
SNP_RESP_RECV_LOCAL_RSPSFWD, 0x60, 0x8, BBOX
SNP_RESP_RECV_LOCAL_RSPXWB, 0x60, 0x10, BBOX
SNP_RESP_RECV_LOCAL_RSPXFWDXWB, 0x60, 0x20, BBOX
SNP_RESP_RECV_LOCAL_RSPCNFLCT, 0x60, 0x40, BBOX
SNP_RESP_RECV_LOCAL_OTHER, 0x60, 0x80, BBOX
STALL_NO_SBO_CREDIT_SBO0_AD, 0x6C, 0x1, BBOX
STALL_NO_SBO_CREDIT_SBO1_AD, 0x6C, 0x2, BBOX
STALL_NO_SBO_CREDIT_SBO0_BL, 0x6C, 0x4, BBOX
STALL_NO_SBO_CREDIT_SBO0_BL, 0x6C, 0x8, BBOX
TAD_REQUESTS_G0_REGION0, 0x1B, 0x1, BBOX
TAD_REQUESTS_G0_REGION1, 0x1B, 0x2, BBOX
TAD_REQUESTS_G0_REGION2, 0x1B, 0x4, BBOX
TAD_REQUESTS_G0_REGION3, 0x1B, 0x8, BBOX
TAD_REQUESTS_G0_REGION4, 0x1B, 0x10, BBOX
TAD_REQUESTS_G0_REGION5, 0x1B, 0x20, BBOX
TAD_REQUESTS_G0_REGION6, 0x1B, 0x40, BBOX
TAD_REQUESTS_G0_REGION7, 0x1B, 0x80, BBOX
TAD_REQUESTS_G1_REGION8, 0x1C, 0x1, BBOX
TAD_REQUESTS_G1_REGION9, 0x1C, 0x2, BBOX
TAD_REQUESTS_G1_REGION10, 0x1C, 0x4, BBOX
TAD_REQUESTS_G1_REGION11, 0x1C, 0x8, BBOX
TRACKER_CYCLES_FULL_GP, 0x2, 0x1, BBOX
TRACKER_CYCLES_FULL_ALL, 0x2, 0x2, BBOX
TRACKER_CYCLES_NE_LOCAL, 0x3, 0x1, BBOX
TRACKER_CYCLES_NE_REMOTE, 0x3, 0x2, BBOX
TRACKER_CYCLES_NE_ALL, 0x3, 0x3, BBOX
TRACKER_OCCUPANCY_READS_LOCAL, 0x4, 0x4, BBOX
TRACKER_OCCUPANCY_READS_REMOTE, 0x4, 0x8, BBOX
TRACKER_OCCUPANCY_WRITES_LOCAL, 0x4, 0x10, BBOX
TRACKER_OCCUPANCY_WRITES_REMOTE, 0x4, 0x20, BBOX
TRACKER_OCCUPANCY_RW_LOCAL, 0x4, 0x14, BBOX
TRACKER_OCCUPANCY_RW_REMOTE, 0x4, 0x28, BBOX
TRACKER_OCCUPANCY_INVITOE_LOCAL, 0x4, 0x40, BBOX
TRACKER_OCCUPANCY_INVITOE_REMOTE, 0x4, 0x80, BBOX
TRACKER_OCCUPANCY_ALL_LOCAL, 0x4, 0x54, BBOX
TRACKER_OCCUPANCY_ALL_REMOTE, 0x4, 0xA8, BBOX
TRACKER_PENDING_OCCUPANCY_LOCAL, 0x5, 0x1, BBOX
TRACKER_PENDING_OCCUPANCY_REMOTE, 0x5, 0x2, BBOX
TRACKER_PENDING_OCCUPANCY_ALL, 0x5, 0x3, BBOX
TXR_AD_CYCLES_FULL_SCHED0, 0x2A, 0x1, BBOX
TXR_AD_CYCLES_FULL_SCHED1, 0x2A, 0x2, BBOX
TXR_AD_CYCLES_FULL_ALL, 0x2A, 0x3, BBOX
TXR_AK, 0xE, 0x0, BBOX
TXR_AK_CYCLES_FULL_SCHED0, 0x32, 0x1, BBOX
TXR_AK_CYCLES_FULL_SCHED1, 0x32, 0x2, BBOX
TXR_AK_CYCLES_FULL_ALL, 0x32, 0x3, BBOX
TXR_BL_DRS_CACHE, 0x10, 0x1, BBOX
TXR_BL_DRS_CORE, 0x10, 0x2, BBOX
TXR_BL_DRS_QPI, 0x10, 0x4, BBOX
TXR_BL_CYCLES_FULL_SCHED0, 0x36, 0x1, BBOX
TXR_BL_CYCLES_FULL_SCHED1, 0x36, 0x2, BBOX
TXR_BL_CYCLES_FULL_ALL, 0x36, 0x3, BBOX
TXR_BL_OCCUPANCY, 0x34, 0x0, BBOX
TXR_STARVED_AK, 0x6D, 0x1, BBOX
TXR_STARVED_BL, 0x6D, 0x2, BBOX
DRAM_CLOCKTICKS, 0x0, 0x0, MBOX
ACT_COUNT_RD, 0x1, 0x1, MBOX
ACT_COUNT_WR, 0x1, 0x2, MBOX
ACT_COUNT_BYP, 0x1, 0x8, MBOX
BYP_CMDS_ACT, 0xA1, 0x1, MBOX
BYP_CMDS_CAS, 0xA1, 0x2, MBOX
BYP_CMDS_PRE, 0xA1, 0x4, MBOX
CAS_COUNT_RD_REG, 0x4, 0x1, MBOX
CAS_COUNT_RD_UNDERFILL, 0x4, 0x2, MBOX
CAS_COUNT_RD, 0x4, 0x3, MBOX
CAS_COUNT_RD_WMM, 0x4, 0x10, MBOX
CAS_COUNT_RD_RMM, 0x4, 0x20, MBOX
CAS_COUNT_WR_WMM, 0x4, 0x4, MBOX
CAS_COUNT_WR_RMM, 0x4, 0x8, MBOX
CAS_COUNT_WR, 0x4, 0xC, MBOX
CAS_COUNT_ALL, 0x4, 0xF, MBOX
DRAM_PRE_ALL, 0x6, 0x0, MBOX
DRAM_REFRESH_PANIC, 0x5, 0x2, MBOX
DRAM_REFRESH_HIGH, 0x5, 0x4, MBOX
ECC_CORRECTABLE_ERRORS, 0x9, 0x0, MBOX
MAJOR_MODES_READ, 0x7, 0x1, MBOX
MAJOR_MODES_WRITE, 0x7, 0x2, MBOX
MAJOR_MODES_PARTIAL, 0x7, 0x3, MBOX
MAJOR_MODES_ISOCH, 0x7, 0x4, MBOX
POWER_CHANNEL_DLLOFF, 0x84, 0x0, MBOX
POWER_CHANNEL_PPD, 0x85, 0x0, MBOX
POWER_CKE_CYCLES_RANK0, 0x83, 0x1, MBOX
POWER_CKE_CYCLES_RANK1, 0x83, 0x2, MBOX
POWER_CKE_CYCLES_RANK2, 0x83, 0x4, MBOX
POWER_CKE_CYCLES_RANK3, 0x83, 0x8, MBOX
POWER_CKE_CYCLES_RANK4, 0x83, 0x10, MBOX
POWER_CKE_CYCLES_RANK5, 0x83, 0x20, MBOX
POWER_CKE_CYCLES_RANK6, 0x83, 0x40, MBOX
POWER_CKE_CYCLES_RANK7, 0x83, 0x80, MBOX
POWER_CRITICAL_THROTTLE_CYCLES, 0x86, 0x0, MBOX
POWER_PCU_THROTTLING, 0x42, 0x0, MBOX
POWER_SELF_REFRESH, 0x43, 0x0, MBOX
POWER_THROTTLE_CYCLES_RANK0, 0x41, 0x1, MBOX
POWER_THROTTLE_CYCLES_RANK1, 0x41, 0x2, MBOX
POWER_THROTTLE_CYCLES_RANK2, 0x41, 0x4, MBOX
POWER_THROTTLE_CYCLES_RANK3, 0x41, 0x8, MBOX
POWER_THROTTLE_CYCLES_RANK4, 0x41, 0x10, MBOX
POWER_THROTTLE_CYCLES_RANK5, 0x41, 0x20, MBOX
POWER_THROTTLE_CYCLES_RANK6, 0x41, 0x40, MBOX
POWER_THROTTLE_CYCLES_RANK7, 0x41, 0x80, MBOX
PREEMPTION_RD_PREEMPT_RD, 0x8, 0x1, MBOX
PREEMPTION_RD_PREEMPT_WR, 0x8, 0x2, MBOX
PRE_COUNT_PAGE_MISS, 0x2, 0x1, MBOX
PRE_COUNT_PAGE_CLOSE, 0x2, 0x2, MBOX
PRE_COUNT_RD, 0x2, 0x4, MBOX
PRE_COUNT_WR, 0x2, 0x8, MBOX
PRE_COUNT_BYP, 0x2, 0x10, MBOX
RD_CAS_PRIO_LOW, 0xA0, 0x1, MBOX
RD_CAS_PRIO_MED, 0xA0, 0x2, MBOX
RD_CAS_PRIO_HIGH, 0xA0, 0x4, MBOX
RD_CAS_PRIO_PANIC, 0xA0, 0x8, MBOX
RD_CAS_RANK0_BANK0, 0xB0, 0x0, MBOX
RD_CAS_RANK0_BANK1, 0xB0, 0x1, MBOX
RD_CAS_RANK0_BANK2, 0xB0, 0x2, MBOX
RD_CAS_RANK0_BANK3, 0xB0, 0x3, MBOX
RD_CAS_RANK0_BANK4, 0xB0, 0x4, MBOX
RD_CAS_RANK0_BANK5, 0xB0, 0x5, MBOX
RD_CAS_RANK0_BANK6, 0xB0, 0x6, MBOX
RD_CAS_RANK0_BANK7, 0xB0, 0x7, MBOX
RD_CAS_RANK0_BANK8, 0xB0, 0x8, MBOX
RD_CAS_RANK0_BANK9, 0xB0, 0x9, MBOX
RD_CAS_RANK0_BANK10, 0xB0, 0xA, MBOX
RD_CAS_RANK0_BANK11, 0xB0, 0xB, MBOX
RD_CAS_RANK0_BANK12, 0xB0, 0xC, MBOX
RD_CAS_RANK0_BANK13, 0xB0, 0xD, MBOX
RD_CAS_RANK0_BANK14, 0xB0, 0xE, MBOX
RD_CAS_RANK0_BANK15, 0xB0, 0xF, MBOX
RD_CAS_RANK0_ALLBANKS, 0xB0, 0x10, MBOX
RD_CAS_RANK0_BANKG0, 0xB0, 0x11, MBOX
RD_CAS_RANK0_BANKG1, 0xB0, 0x12, MBOX
RD_CAS_RANK0_BANKG2, 0xB0, 0x13, MBOX
RD_CAS_RANK0_BANKG3, 0xB0, 0x14, MBOX
RD_CAS_RANK1_BANK0, 0xB1, 0x0, MBOX
RD_CAS_RANK1_BANK1, 0xB1, 0x1, MBOX
RD_CAS_RANK1_BANK2, 0xB1, 0x2, MBOX
RD_CAS_RANK1_BANK3, 0xB1, 0x3, MBOX
RD_CAS_RANK1_BANK4, 0xB1, 0x4, MBOX
RD_CAS_RANK1_BANK5, 0xB1, 0x5, MBOX
RD_CAS_RANK1_BANK6, 0xB1, 0x6, MBOX
RD_CAS_RANK1_BANK7, 0xB1, 0x7, MBOX
RD_CAS_RANK1_BANK8, 0xB1, 0x8, MBOX
RD_CAS_RANK1_BANK9, 0xB1, 0x9, MBOX
RD_CAS_RANK1_BANK10, 0xB1, 0xA, MBOX
RD_CAS_RANK1_BANK11, 0xB1, 0xB, MBOX
RD_CAS_RANK1_BANK12, 0xB1, 0xC, MBOX
RD_CAS_RANK1_BANK13, 0xB1, 0xD, MBOX
RD_CAS_RANK1_BANK14, 0xB1, 0xE, MBOX
RD_CAS_RANK1_BANK15, 0xB1, 0xF, MBOX
RD_CAS_RANK1_ALLBANKS, 0xB1, 0x10, MBOX
RD_CAS_RANK1_BANKG0, 0xB1, 0x11, MBOX
RD_CAS_RANK1_BANKG1, 0xB1, 0x12, MBOX
RD_CAS_RANK1_BANKG2, 0xB1, 0x13, MBOX
RD_CAS_RANK1_BANKG3, 0xB1, 0x14, MBOX
RD_CAS_RANK2_BANK0, 0xB2, 0x0, MBOX
RD_CAS_RANK2_BANK1, 0xB2, 0x1, MBOX
RD_CAS_RANK2_BANK2, 0xB2, 0x2, MBOX
RD_CAS_RANK2_BANK3, 0xB2, 0x3, MBOX
RD_CAS_RANK2_BANK4, 0xB2, 0x4, MBOX
RD_CAS_RANK2_BANK5, 0xB2, 0x5, MBOX
RD_CAS_RANK2_BANK6, 0xB2, 0x6, MBOX
RD_CAS_RANK2_BANK7, 0xB2, 0x7, MBOX
RD_CAS_RANK2_BANK8, 0xB2, 0x8, MBOX
RD_CAS_RANK2_BANK9, 0xB2, 0x9, MBOX
RD_CAS_RANK2_BANK10, 0xB2, 0xA, MBOX
RD_CAS_RANK2_BANK11, 0xB2, 0xB, MBOX
RD_CAS_RANK2_BANK12, 0xB2, 0xC, MBOX
RD_CAS_RANK2_BANK13, 0xB2, 0xD, MBOX
RD_CAS_RANK2_BANK14, 0xB2, 0xE, MBOX
RD_CAS_RANK2_BANK15, 0xB2, 0xF, MBOX
RD_CAS_RANK2_ALLBANKS, 0xB2, 0x10, MBOX
RD_CAS_RANK2_BANKG0, 0xB2, 0x11, MBOX
RD_CAS_RANK2_BANKG1, 0xB2, 0x12, MBOX
RD_CAS_RANK2_BANKG2, 0xB2, 0x13, MBOX
RD_CAS_RANK2_BANKG3, 0xB2, 0x14, MBOX
RD_CAS_RANK3_BANK0, 0xB3, 0x0, MBOX
RD_CAS_RANK3_BANK1, 0xB3, 0x1, MBOX
RD_CAS_RANK3_BANK2, 0xB3, 0x2, MBOX
RD_CAS_RANK3_BANK3, 0xB3, 0x3, MBOX
RD_CAS_RANK3_BANK4, 0xB3, 0x4, MBOX
RD_CAS_RANK3_BANK5, 0xB3, 0x5, MBOX
RD_CAS_RANK3_BANK6, 0xB3, 0x6, MBOX
RD_CAS_RANK3_BANK7, 0xB3, 0x7, MBOX
RD_CAS_RANK3_BANK8, 0xB3, 0x8, MBOX
RD_CAS_RANK3_BANK9, 0xB3, 0x9, MBOX
RD_CAS_RANK3_BANK10, 0xB3, 0xA, MBOX
RD_CAS_RANK3_BANK11, 0xB3, 0xB, MBOX
RD_CAS_RANK3_BANK12, 0xB3, 0xC, MBOX
RD_CAS_RANK3_BANK13, 0xB3, 0xD, MBOX
RD_CAS_RANK3_BANK14, 0xB3, 0xE, MBOX
RD_CAS_RANK3_BANK15, 0xB3, 0xF, MBOX
RD_CAS_RANK3_ALLBANKS, 0xB3, 0x10, MBOX
RD_CAS_RANK3_BANKG0, 0xB3, 0x11, MBOX
RD_CAS_RANK3_BANKG1, 0xB3, 0x12, MBOX
RD_CAS_RANK3_BANKG2, 0xB3, 0x13, MBOX
RD_CAS_RANK3_BANKG3, 0xB3, 0x14, MBOX
RD_CAS_RANK4_BANK0, 0xB4, 0x0, MBOX
RD_CAS_RANK4_BANK1, 0xB4, 0x1, MBOX
RD_CAS_RANK4_BANK2, 0xB4, 0x2, MBOX
RD_CAS_RANK4_BANK3, 0xB4, 0x3, MBOX
RD_CAS_RANK4_BANK4, 0xB4, 0x4, MBOX
RD_CAS_RANK4_BANK5, 0xB4, 0x5, MBOX
RD_CAS_RANK4_BANK6, 0xB4, 0x6, MBOX
RD_CAS_RANK4_BANK7, 0xB4, 0x7, MBOX
RD_CAS_RANK4_BANK8, 0xB4, 0x8, MBOX
RD_CAS_RANK4_BANK9, 0xB4, 0x9, MBOX
RD_CAS_RANK4_BANK10, 0xB4, 0xA, MBOX
RD_CAS_RANK4_BANK11, 0xB4, 0xB, MBOX
RD_CAS_RANK4_BANK12, 0xB4, 0xC, MBOX
RD_CAS_RANK4_BANK13, 0xB4, 0xD, MBOX
RD_CAS_RANK4_BANK14, 0xB4, 0xE, MBOX
RD_CAS_RANK4_BANK15, 0xB4, 0xF, MBOX
RD_CAS_RANK4_ALLBANKS, 0xB4, 0x10, MBOX
RD_CAS_RANK4_BANKG0, 0xB4, 0x11, MBOX
RD_CAS_RANK4_BANKG1, 0xB4, 0x12, MBOX
RD_CAS_RANK4_BANKG2, 0xB4, 0x13, MBOX
RD_CAS_RANK4_BANKG3, 0xB4, 0x14, MBOX
RD_CAS_RANK5_BANK0, 0xB5, 0x0, MBOX
RD_CAS_RANK5_BANK1, 0xB5, 0x1, MBOX
RD_CAS_RANK5_BANK2, 0xB5, 0x2, MBOX
RD_CAS_RANK5_BANK3, 0xB5, 0x3, MBOX
RD_CAS_RANK5_BANK4, 0xB5, 0x4, MBOX
RD_CAS_RANK5_BANK5, 0xB5, 0x5, MBOX
RD_CAS_RANK5_BANK6, 0xB5, 0x6, MBOX
RD_CAS_RANK5_BANK7, 0xB5, 0x7, MBOX
RD_CAS_RANK5_BANK8, 0xB5, 0x8, MBOX
RD_CAS_RANK5_BANK9, 0xB5, 0x9, MBOX
RD_CAS_RANK5_BANK10, 0xB5, 0xA, MBOX
RD_CAS_RANK5_BANK11, 0xB5, 0xB, MBOX
RD_CAS_RANK5_BANK12, 0xB5, 0xC, MBOX
RD_CAS_RANK5_BANK13, 0xB5, 0xD, MBOX
RD_CAS_RANK5_BANK14, 0xB5, 0xE, MBOX
RD_CAS_RANK5_BANK15, 0xB5, 0xF, MBOX
RD_CAS_RANK5_ALLBANKS, 0xB5, 0x10, MBOX
RD_CAS_RANK5_BANKG0, 0xB5, 0x11, MBOX
RD_CAS_RANK5_BANKG1, 0xB5, 0x12, MBOX
RD_CAS_RANK5_BANKG2, 0xB5, 0x13, MBOX
RD_CAS_RANK5_BANKG3, 0xB5, 0x14, MBOX
RD_CAS_RANK6_BANK0, 0xB6, 0x0, MBOX
RD_CAS_RANK6_BANK1, 0xB6, 0x1, MBOX
RD_CAS_RANK6_BANK2, 0xB6, 0x2, MBOX
RD_CAS_RANK6_BANK3, 0xB6, 0x3, MBOX
RD_CAS_RANK6_BANK4, 0xB6, 0x4, MBOX
RD_CAS_RANK6_BANK5, 0xB6, 0x5, MBOX
RD_CAS_RANK6_BANK6, 0xB6, 0x6, MBOX
RD_CAS_RANK6_BANK7, 0xB6, 0x7, MBOX
RD_CAS_RANK6_BANK8, 0xB6, 0x8, MBOX
RD_CAS_RANK6_BANK9, 0xB6, 0x9, MBOX
RD_CAS_RANK6_BANK10, 0xB6, 0xA, MBOX
RD_CAS_RANK6_BANK11, 0xB6, 0xB, MBOX
RD_CAS_RANK6_BANK12, 0xB6, 0xC, MBOX
RD_CAS_RANK6_BANK13, 0xB6, 0xD, MBOX
RD_CAS_RANK6_BANK14, 0xB6, 0xE, MBOX
RD_CAS_RANK6_BANK15, 0xB6, 0xF, MBOX
RD_CAS_RANK6_ALLBANKS, 0xB6, 0x10, MBOX
RD_CAS_RANK6_BANKG0, 0xB6, 0x11, MBOX
RD_CAS_RANK6_BANKG1, 0xB6, 0x12, MBOX
RD_CAS_RANK6_BANKG2, 0xB6, 0x13, MBOX
RD_CAS_RANK6_BANKG3, 0xB6, 0x14, MBOX
RD_CAS_RANK7_BANK0, 0xB7, 0x0, MBOX
RD_CAS_RANK7_BANK1, 0xB7, 0x1, MBOX
RD_CAS_RANK7_BANK2, 0xB7, 0x2, MBOX
RD_CAS_RANK7_BANK3, 0xB7, 0x3, MBOX
RD_CAS_RANK7_BANK4, 0xB7, 0x4, MBOX
RD_CAS_RANK7_BANK5, 0xB7, 0x5, MBOX
RD_CAS_RANK7_BANK6, 0xB7, 0x6, MBOX
RD_CAS_RANK7_BANK7, 0xB7, 0x7, MBOX
RD_CAS_RANK7_BANK8, 0xB7, 0x8, MBOX
RD_CAS_RANK7_BANK9, 0xB7, 0x9, MBOX
RD_CAS_RANK7_BANK10, 0xB7, 0xA, MBOX
RD_CAS_RANK7_BANK11, 0xB7, 0xB, MBOX
RD_CAS_RANK7_BANK12, 0xB7, 0xC, MBOX
RD_CAS_RANK7_BANK13, 0xB7, 0xD, MBOX
RD_CAS_RANK7_BANK14, 0xB7, 0xE, MBOX
RD_CAS_RANK7_BANK15, 0xB7, 0xF, MBOX
RD_CAS_RANK7_ALLBANKS, 0xB7, 0x10, MBOX
RD_CAS_RANK7_BANKG0, 0xB7, 0x11, MBOX
RD_CAS_RANK7_BANKG1, 0xB7, 0x12, MBOX
RD_CAS_RANK7_BANKG2, 0xB7, 0x13, MBOX
RD_CAS_RANK7_BANKG3, 0xB7, 0x14, MBOX
RPQ_CYCLES_NE, 0x11, 0x0, MBOX
RPQ_INSERTS, 0x10, 0x0, MBOX
RPQ_CYCLES_FULL, 0x12, 0x0, MBOX
VMSE_MXB_WR_OCCUPANCY, 0x91, 0x0, MBOX
VMSE_WR_PUSH_WMM, 0x90, 0x1, MBOX
VMSE_WR_PUSH_RMM, 0x90, 0x2, MBOX
WMM_TO_RMM_LOW_THRESH, 0xC0, 0x1, MBOX
WMM_TO_RMM_STARVE, 0xC0, 0x2, MBOX
WMM_TO_RMM_VMSE_RETRY, 0xC0, 0x4, MBOX
WPQ_INSERTS, 0x20, 0x0, MBOX
WPQ_CYCLES_FULL, 0x22, 0x0, MBOX
WPQ_CYCLES_NE, 0x21, 0x0, MBOX
WPQ_READ_HIT, 0x23, 0x0, MBOX
WPQ_WRITE_HIT, 0x24, 0x0, MBOX
WRONG_MM, 0xC1, 0x0, MBOX
WR_CAS_RANK0_BANK0, 0xB8, 0x0, MBOX
WR_CAS_RANK0_BANK1, 0xB8, 0x1, MBOX
WR_CAS_RANK0_BANK2, 0xB8, 0x2, MBOX
WR_CAS_RANK0_BANK3, 0xB8, 0x3, MBOX
WR_CAS_RANK0_BANK4, 0xB8, 0x4, MBOX
WR_CAS_RANK0_BANK5, 0xB8, 0x5, MBOX
WR_CAS_RANK0_BANK6, 0xB8, 0x6, MBOX
WR_CAS_RANK0_BANK7, 0xB8, 0x7, MBOX
WR_CAS_RANK0_BANK8, 0xB8, 0x8, MBOX
WR_CAS_RANK0_BANK9, 0xB8, 0x9, MBOX
WR_CAS_RANK0_BANK10, 0xB8, 0xA, MBOX
WR_CAS_RANK0_BANK11, 0xB8, 0xB, MBOX
WR_CAS_RANK0_BANK12, 0xB8, 0xC, MBOX
WR_CAS_RANK0_BANK13, 0xB8, 0xD, MBOX
WR_CAS_RANK0_BANK14, 0xB8, 0xE, MBOX
WR_CAS_RANK0_BANK15, 0xB8, 0xF, MBOX
WR_CAS_RANK0_ALLBANKS, 0xB8, 0x10, MBOX
WR_CAS_RANK0_BANKG0, 0xB8, 0x11, MBOX
WR_CAS_RANK0_BANKG1, 0xB8, 0x12, MBOX
WR_CAS_RANK0_BANKG2, 0xB8, 0x13, MBOX
WR_CAS_RANK0_BANKG3, 0xB8, 0x14, MBOX
WR_CAS_RANK1_BANK0, 0xB9, 0x0, MBOX
WR_CAS_RANK1_BANK1, 0xB9, 0x1, MBOX
WR_CAS_RANK1_BANK2, 0xB9, 0x2, MBOX
WR_CAS_RANK1_BANK3, 0xB9, 0x3, MBOX
WR_CAS_RANK1_BANK4, 0xB9, 0x4, MBOX
WR_CAS_RANK1_BANK5, 0xB9, 0x5, MBOX
WR_CAS_RANK1_BANK6, 0xB9, 0x6, MBOX
WR_CAS_RANK1_BANK7, 0xB9, 0x7, MBOX
WR_CAS_RANK1_BANK8, 0xB9, 0x8, MBOX
WR_CAS_RANK1_BANK9, 0xB9, 0x9, MBOX
WR_CAS_RANK1_BANK10, 0xB9, 0xA, MBOX
WR_CAS_RANK1_BANK11, 0xB9, 0xB, MBOX
WR_CAS_RANK1_BANK12, 0xB9, 0xC, MBOX
WR_CAS_RANK1_BANK13, 0xB9, 0xD, MBOX
WR_CAS_RANK1_BANK14, 0xB9, 0xE, MBOX
WR_CAS_RANK1_BANK15, 0xB9, 0xF, MBOX
WR_CAS_RANK1_ALLBANKS, 0xB9, 0x10, MBOX
WR_CAS_RANK1_BANKG0, 0xB9, 0x11, MBOX
WR_CAS_RANK1_BANKG1, 0xB9, 0x12, MBOX
WR_CAS_RANK1_BANKG2, 0xB9, 0x13, MBOX
WR_CAS_RANK1_BANKG3, 0xB9, 0x14, MBOX
WR_CAS_RANK2_BANK0, 0xBA, 0x0, MBOX
WR_CAS_RANK2_BANK1, 0xBA, 0x1, MBOX
WR_CAS_RANK2_BANK2, 0xBA, 0x2, MBOX
WR_CAS_RANK2_BANK3, 0xBA, 0x3, MBOX
WR_CAS_RANK2_BANK4, 0xBA, 0x4, MBOX
WR_CAS_RANK2_BANK5, 0xBA, 0x5, MBOX
WR_CAS_RANK2_BANK6, 0xBA, 0x6, MBOX
WR_CAS_RANK2_BANK7, 0xBA, 0x7, MBOX
WR_CAS_RANK2_BANK8, 0xBA, 0x8, MBOX
WR_CAS_RANK2_BANK9, 0xBA, 0x9, MBOX
WR_CAS_RANK2_BANK10, 0xBA, 0xA, MBOX
WR_CAS_RANK2_BANK11, 0xBA, 0xB, MBOX
WR_CAS_RANK2_BANK12, 0xBA, 0xC, MBOX
WR_CAS_RANK2_BANK13, 0xBA, 0xD, MBOX
WR_CAS_RANK2_BANK14, 0xBA, 0xE, MBOX
WR_CAS_RANK2_BANK15, 0xBA, 0xF, MBOX
WR_CAS_RANK2_ALLBANKS, 0xBA, 0x10, MBOX
WR_CAS_RANK2_BANKG0, 0xBA, 0x11, MBOX
WR_CAS_RANK2_BANKG1, 0xBA, 0x12, MBOX
WR_CAS_RANK2_BANKG2, 0xBA, 0x13, MBOX
WR_CAS_RANK2_BANKG3, 0xBA, 0x14, MBOX
WR_CAS_RANK3_BANK0, 0xBB, 0x0, MBOX
WR_CAS_RANK3_BANK1, 0xBB, 0x1, MBOX
WR_CAS_RANK3_BANK2, 0xBB, 0x2, MBOX
WR_CAS_RANK3_BANK3, 0xBB, 0x3, MBOX
WR_CAS_RANK3_BANK4, 0xBB, 0x4, MBOX
WR_CAS_RANK3_BANK5, 0xBB, 0x5, MBOX
WR_CAS_RANK3_BANK6, 0xBB, 0x6, MBOX
WR_CAS_RANK3_BANK7, 0xBB, 0x7, MBOX
WR_CAS_RANK3_BANK8, 0xBB, 0x8, MBOX
WR_CAS_RANK3_BANK9, 0xBB, 0x9, MBOX
WR_CAS_RANK3_BANK10, 0xBB, 0xA, MBOX
WR_CAS_RANK3_BANK11, 0xBB, 0xB, MBOX
WR_CAS_RANK3_BANK12, 0xBB, 0xC, MBOX
WR_CAS_RANK3_BANK13, 0xBB, 0xD, MBOX
WR_CAS_RANK3_BANK14, 0xBB, 0xE, MBOX
WR_CAS_RANK3_BANK15, 0xBB, 0xF, MBOX
WR_CAS_RANK3_ALLBANKS, 0xBB, 0x10, MBOX
WR_CAS_RANK3_BANKG0, 0xBB, 0x11, MBOX
WR_CAS_RANK3_BANKG1, 0xBB, 0x12, MBOX
WR_CAS_RANK3_BANKG2, 0xBB, 0x13, MBOX
WR_CAS_RANK3_BANKG3, 0xBB, 0x14, MBOX
WR_CAS_RANK4_BANK0, 0xBC, 0x0, MBOX
WR_CAS_RANK4_BANK1, 0xBC, 0x1, MBOX
WR_CAS_RANK4_BANK2, 0xBC, 0x2, MBOX
WR_CAS_RANK4_BANK3, 0xBC, 0x3, MBOX
WR_CAS_RANK4_BANK4, 0xBC, 0x4, MBOX
WR_CAS_RANK4_BANK5, 0xBC, 0x5, MBOX
WR_CAS_RANK4_BANK6, 0xBC, 0x6, MBOX
WR_CAS_RANK4_BANK7, 0xBC, 0x7, MBOX
WR_CAS_RANK4_BANK8, 0xBC, 0x8, MBOX
WR_CAS_RANK4_BANK9, 0xBC, 0x9, MBOX
WR_CAS_RANK4_BANK10, 0xBC, 0xA, MBOX
WR_CAS_RANK4_BANK11, 0xBC, 0xB, MBOX
WR_CAS_RANK4_BANK12, 0xBC, 0xC, MBOX
WR_CAS_RANK4_BANK13, 0xBC, 0xD, MBOX
WR_CAS_RANK4_BANK14, 0xBC, 0xE, MBOX
WR_CAS_RANK4_BANK15, 0xBC, 0xF, MBOX
WR_CAS_RANK4_ALLBANKS, 0xBC, 0x10, MBOX
WR_CAS_RANK4_BANKG0, 0xBC, 0x11, MBOX
WR_CAS_RANK4_BANKG1, 0xBC, 0x12, MBOX
WR_CAS_RANK4_BANKG2, 0xBC, 0x13, MBOX
WR_CAS_RANK4_BANKG3, 0xBC, 0x14, MBOX
WR_CAS_RANK5_BANK0, 0xBD, 0x0, MBOX
WR_CAS_RANK5_BANK1, 0xBD, 0x1, MBOX
WR_CAS_RANK5_BANK2, 0xBD, 0x2, MBOX
WR_CAS_RANK5_BANK3, 0xBD, 0x3, MBOX
WR_CAS_RANK5_BANK4, 0xBD, 0x4, MBOX
WR_CAS_RANK5_BANK5, 0xBD, 0x5, MBOX
WR_CAS_RANK5_BANK6, 0xBD, 0x6, MBOX
WR_CAS_RANK5_BANK7, 0xBD, 0x7, MBOX
WR_CAS_RANK5_BANK8, 0xBD, 0x8, MBOX
WR_CAS_RANK5_BANK9, 0xBD, 0x9, MBOX
WR_CAS_RANK5_BANK10, 0xBD, 0xA, MBOX
WR_CAS_RANK5_BANK11, 0xBD, 0xB, MBOX
WR_CAS_RANK5_BANK12, 0xBD, 0xC, MBOX
WR_CAS_RANK5_BANK13, 0xBD, 0xD, MBOX
WR_CAS_RANK5_BANK14, 0xBD, 0xE, MBOX
WR_CAS_RANK5_BANK15, 0xBD, 0xF, MBOX
WR_CAS_RANK5_ALLBANKS, 0xBD, 0x10, MBOX
WR_CAS_RANK5_BANKG0, 0xBD, 0x11, MBOX
WR_CAS_RANK5_BANKG1, 0xBD, 0x12, MBOX
WR_CAS_RANK5_BANKG2, 0xBD, 0x13, MBOX
WR_CAS_RANK5_BANKG3, 0xBD, 0x14, MBOX
WR_CAS_RANK6_BANK0, 0xBE, 0x0, MBOX
WR_CAS_RANK6_BANK1, 0xBE, 0x1, MBOX
WR_CAS_RANK6_BANK2, 0xBE, 0x2, MBOX
WR_CAS_RANK6_BANK3, 0xBE, 0x3, MBOX
WR_CAS_RANK6_BANK4, 0xBE, 0x4, MBOX
WR_CAS_RANK6_BANK5, 0xBE, 0x5, MBOX
WR_CAS_RANK6_BANK6, 0xBE, 0x6, MBOX
WR_CAS_RANK6_BANK7, 0xBE, 0x7, MBOX
WR_CAS_RANK6_BANK8, 0xBE, 0x8, MBOX
WR_CAS_RANK6_BANK9, 0xBE, 0x9, MBOX
WR_CAS_RANK6_BANK10, 0xBE, 0xA, MBOX
WR_CAS_RANK6_BANK11, 0xBE, 0xB, MBOX
WR_CAS_RANK6_BANK12, 0xBE, 0xC, MBOX
WR_CAS_RANK6_BANK13, 0xBE, 0xD, MBOX
WR_CAS_RANK6_BANK14, 0xBE, 0xE, MBOX
WR_CAS_RANK6_BANK15, 0xBE, 0xF, MBOX
WR_CAS_RANK6_ALLBANKS, 0xBE, 0x10, MBOX
WR_CAS_RANK6_BANKG0, 0xBE, 0x11, MBOX
WR_CAS_RANK6_BANKG1, 0xBE, 0x12, MBOX
WR_CAS_RANK6_BANKG2, 0xBE, 0x13, MBOX
WR_CAS_RANK6_BANKG3, 0xBE, 0x14, MBOX
WR_CAS_RANK7_BANK0, 0xBF, 0x0, MBOX
WR_CAS_RANK7_BANK1, 0xBF, 0x1, MBOX
WR_CAS_RANK7_BANK2, 0xBF, 0x2, MBOX
WR_CAS_RANK7_BANK3, 0xBF, 0x3, MBOX
WR_CAS_RANK7_BANK4, 0xBF, 0x4, MBOX
WR_CAS_RANK7_BANK5, 0xBF, 0x5, MBOX
WR_CAS_RANK7_BANK6, 0xBF, 0x6, MBOX
WR_CAS_RANK7_BANK7, 0xBF, 0x7, MBOX
WR_CAS_RANK7_BANK8, 0xBF, 0x8, MBOX
WR_CAS_RANK7_BANK9, 0xBF, 0x9, MBOX
WR_CAS_RANK7_BANK10, 0xBF, 0xA, MBOX
WR_CAS_RANK7_BANK11, 0xBF, 0xB, MBOX
WR_CAS_RANK7_BANK12, 0xBF, 0xC, MBOX
WR_CAS_RANK7_BANK13, 0xBF, 0xD, MBOX
WR_CAS_RANK7_BANK14, 0xBF, 0xE, MBOX
WR_CAS_RANK7_BANK15, 0xBF, 0xF, MBOX
WR_CAS_RANK7_ALLBANKS, 0xBF, 0x10, MBOX
WR_CAS_RANK7_BANKG0, 0xBF, 0x11, MBOX
WR_CAS_RANK7_BANKG1, 0xBF, 0x12, MBOX
WR_CAS_RANK7_BANKG2, 0xBF, 0x13, MBOX
WR_CAS_RANK7_BANKG3, 0xBF, 0x14, MBOX
PBOX_CLOCKTICKS, 0x1, 0x0, PBOX
IIO_CREDIT_PRQ_QPI0, 0x2D, 0x1, PBOX0|PBOX1
IIO_CREDIT_PRQ_QPI1, 0x2D, 0x2, PBOX0|PBOX1
IIO_CREDIT_ISOCH_QPI0, 0x2D, 0x4, PBOX0|PBOX1
IIO_CREDIT_ISOCH_QPI1, 0x2D, 0x8, PBOX0|PBOX1
RING_AD_USED_CW_EVEN, 0x7, 0x1, PBOX
RING_AD_USED_CW_ODD, 0x7, 0x2, PBOX
RING_AD_USED_CW, 0x7, 0x3, PBOX
RING_AD_USED_CCW_EVEN, 0x7, 0x4, PBOX
RING_AD_USED_CCW_ODD, 0x7, 0x8, PBOX
RING_AD_USED_CCW, 0x7, 0xC, PBOX
RING_AK_BOUNCES_UP, 0x12, 0x1, PBOX
RING_AK_BOUNCES_DN, 0x12, 0x2, PBOX
RING_AK_USED_CW_EVEN, 0x8, 0x1, PBOX
RING_AK_USED_CW_ODD, 0x8, 0x2, PBOX
RING_AK_USED_CW, 0x8, 0x3, PBOX
RING_AK_USED_CCW_EVEN, 0x8, 0x4, PBOX
RING_AK_USED_CCW_ODD, 0x8, 0x8, PBOX
RING_AK_USED_CCW, 0x8, 0xC, PBOX
RING_BL_USED_CW_EVEN, 0x9, 0x1, PBOX
RING_BL_USED_CW_ODD, 0x9, 0x2, PBOX
RING_BL_USED_CW, 0x9, 0x3, PBOX
RING_BL_USED_CCW_EVEN, 0x9, 0x4, PBOX
RING_BL_USED_CCW_ODD, 0x9, 0x8, PBOX
RING_BL_USED_CCW, 0x9, 0xC, PBOX
RING_IV_USED_CW, 0xA, 0x3, PBOX
RING_IV_USED_CCW, 0xA, 0xC, PBOX
RING_IV_USED_ANY, 0xA, 0xF, PBOX
RXR_CYCLES_NE_NCB, 0x10, 0x10, PBOX0|PBOX1
RXR_CYCLES_NE_NCS, 0x10, 0x20, PBOX0|PBOX1
RXR_INSERTS_NCB, 0x11, 0x10, PBOX0|PBOX1
RXR_INSERTS_NCS, 0x11, 0x20, PBOX0|PBOX1
RXR_OCCUPANCY_DRS, 0x13, 0x8, PBOX0
TXR_CYCLES_FULL_AD, 0x25, 0x1, PBOX0
TXR_CYCLES_FULL_AK, 0x25, 0x2, PBOX0
TXR_CYCLES_FULL_BL, 0x25, 0x4, PBOX0
TXR_CYCLES_NE_AD, 0x23, 0x1, PBOX0
TXR_CYCLES_NE_AK, 0x23, 0x2, PBOX0
TXR_CYCLES_NE_BL, 0x23, 0x4, PBOX0
TXR_NACK_CW_DN_AD, 0x26, 0x1, PBOX0|PBOX1
TXR_NACK_CW_DN_BL, 0x26, 0x2, PBOX0|PBOX1
TXR_NACK_CW_DN_AK, 0x26, 0x4, PBOX0|PBOX1
TXR_NACK_CW_UP_AD, 0x26, 0x8, PBOX0|PBOX1
TXR_NACK_CW_UP_BL, 0x26, 0x10, PBOX0|PBOX1
TXR_NACK_CW_UP_AK, 0x26, 0x20, PBOX0|PBOX1
SBO0_CREDITS_ACQUIRED_AD, 0x28, 0x1, PBOX0|PBOX1
SBO0_CREDITS_ACQUIRED_BL, 0x28, 0x2, PBOX0|PBOX1
STALL_NO_SBO_CREDIT_SBO0_AD, 0x2C, 0x1, PBOX0|PBOX1
STALL_NO_SBO_CREDIT_SBO1_AD, 0x2C, 0x2, PBOX0|PBOX1
STALL_NO_SBO_CREDIT_SBO0_BL, 0x2C, 0x4, PBOX0|PBOX1
STALL_NO_SBO_CREDIT_SBO0_BL, 0x2C, 0x8, PBOX0|PBOX1
CACHE_TOTAL_OCCUPANCY_ANY, 0x12, 0x1, IBOX
CACHE_TOTAL_OCCUPANCY_SOURCE, 0x12, 0x2, IBOX
COHERENT_OPS_PCIRDCUR, 0x13, 0x1, IBOX
COHERENT_OPS_CRD, 0x13, 0x2, IBOX
COHERENT_OPS_DRD, 0x13, 0x4, IBOX
COHERENT_OPS_RFO, 0x13, 0x8, IBOX
COHERENT_OPS_PCITOM, 0x13, 0x10, IBOX
COHERENT_OPS_PCIDCAHINT, 0x13, 0x20, IBOX
COHERENT_OPS_WBMTOI, 0x13, 0x40, IBOX
COHERENT_OPS_CLFLUSH, 0x13, 0x80, IBOX
MISC0_FAST_REQ, 0x14, 0x1, IBOX
MISC0_FAST_REJ, 0x14, 0x2, IBOX
MISC0_2ND_RD_INSERT, 0x14, 0x4, IBOX
MISC0_2ND_WR_INSERT, 0x14, 0x8, IBOX
MISC0_2ND_ATOMIC_INSERT, 0x14, 0x10, IBOX
MISC0_FAST_XFER, 0x14, 0x20, IBOX
MISC0_PF_ACK_HINT, 0x14, 0x40, IBOX
MISC0_PF_TIMEOUT, 0x14, 0x80, IBOX
MISC1_SLOW_I, 0x15, 0x1, IBOX
MISC1_SLOW_S, 0x15, 0x2, IBOX
MISC1_SLOW_E, 0x15, 0x4, IBOX
MISC1_SLOW_M, 0x15, 0x8, IBOX
MISC1_LOST_FWD, 0x15, 0x10, IBOX
MISC1_SEC_RCVD_INVLD, 0x15, 0x20, IBOX
MISC1_SEC_RCVD_VLD, 0x15, 0x40, IBOX
MISC1_DATA_THROTTLE, 0x15, 0x80, IBOX
SNOOP_RESP_MISS, 0x17, 0x1, IBOX
SNOOP_RESP_HIT_I, 0x17, 0x2, IBOX
SNOOP_RESP_HIT_ES, 0x17, 0x4, IBOX
SNOOP_RESP_HIT_M, 0x17, 0x8, IBOX
SNOOP_RESP_SNPCODE, 0x17, 0x10, IBOX
SNOOP_RESP_SNPDATA, 0x17, 0x20, IBOX
SNOOP_RESP_SNPINV, 0x17, 0x40, IBOX
TRANSACTIONS_READS, 0x16, 0x1, IBOX
TRANSACTIONS_WRITES, 0x16, 0x2, IBOX
TRANSACTIONS_RD_PREF, 0x16, 0x4, IBOX
TRANSACTIONS_WR_PREF, 0x16, 0x8, IBOX
TRANSACTIONS_ALL_READS, 0x16, 0x5, IBOX
TRANSACTIONS_ALL_WRITES, 0x16, 0xA, IBOX
TRANSACTIONS_ATOMIC, 0x16, 0x10, IBOX
TRANSACTIONS_OTHER, 0x16, 0x20, IBOX
TRANSACTIONS_ORDERINGQ, 0x16, 0x40, IBOX
RXR_AK_INSERTS, 0xA, 0x0, IBOX
RXR_BL_DRS_CYCLES_FULL, 0x4, 0x0, IBOX
RXR_BL_DRS_INSERTS, 0x1, 0x0, IBOX
RXR_BL_DRS_OCCUPANCY, 0x7, 0x0, IBOX
RXR_BL_NCB_CYCLES_FULL, 0x5, 0x0, IBOX
RXR_BL_NCB_INSERTS, 0x2, 0x0, IBOX
RXR_BL_NCB_OCCUPANCY, 0x8, 0x0, IBOX
RXR_BL_NCS_CYCLES_FULL, 0x6, 0x0, IBOX
RXR_BL_NCS_INSERTS, 0x3, 0x0, IBOX
RXR_BL_NCS_OCCUPANCY, 0x9, 0x0, IBOX
TXR_AD_STALL_CREDIT_CYCLES, 0x18, 0x0, IBOX
TXR_BL_STALL_CREDIT_CYCLES, 0x19, 0x0, IBOX
TXR_DATA_INSERTS_NCB, 0xE, 0x0, IBOX
TXR_DATA_INSERTS_NCS, 0xF, 0x0, IBOX
TXR_REQUEST_OCCUPANCY, 0xD, 0x0, IBOX
RBOX_CLOCKTICK, 0x1, 0x0, RBOX
C_HI_AD_CREDITS_EMPTY_CBO8, 0x1F, 0x1, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
C_HI_AD_CREDITS_EMPTY_CBO9, 0x1F, 0x2, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
C_HI_AD_CREDITS_EMPTY_CBO10, 0x1F, 0x4, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
C_HI_AD_CREDITS_EMPTY_CBO11, 0x1F, 0x8, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
C_HI_AD_CREDITS_EMPTY_CBO12, 0x1F, 0x10, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
C_HI_AD_CREDITS_EMPTY_CBO13, 0x1F, 0x20, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
C_HI_AD_CREDITS_EMPTY_CBO14_16, 0x1F, 0x40, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
C_HI_AD_CREDITS_EMPTY_CBO15_17, 0x1F, 0x80, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
C_LO_AD_CREDITS_EMPTY_CBO0, 0x22, 0x1, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
C_LO_AD_CREDITS_EMPTY_CBO1, 0x22, 0x2, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
C_LO_AD_CREDITS_EMPTY_CBO2, 0x22, 0x4, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
C_LO_AD_CREDITS_EMPTY_CBO3, 0x22, 0x8, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
C_LO_AD_CREDITS_EMPTY_CBO4, 0x22, 0x10, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
C_LO_AD_CREDITS_EMPTY_CBO5, 0x22, 0x20, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
C_LO_AD_CREDITS_EMPTY_CBO6, 0x22, 0x40, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
C_LO_AD_CREDITS_EMPTY_CBO7, 0x22, 0x80, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
HA_R2_BL_CREDITS_EMPTY_HA0, 0x2D, 0x1, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
HA_R2_BL_CREDITS_EMPTY_HA1, 0x2D, 0x2, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
HA_R2_BL_CREDITS_EMPTY_R2_NCB, 0x2D, 0x4, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
HA_R2_BL_CREDITS_EMPTY_R2_NCS, 0x2D, 0x8, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
QPI0_AD_CREDITS_EMPTY_VNA, 0x20, 0x1, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
QPI0_AD_CREDITS_EMPTY_VN0_HOM, 0x20, 0x2, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
QPI0_AD_CREDITS_EMPTY_VN0_SNP, 0x20, 0x4, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
QPI0_AD_CREDITS_EMPTY_VN0_NDR, 0x20, 0x8, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
QPI0_AD_CREDITS_EMPTY_VN1_HOM, 0x20, 0x10, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
QPI0_AD_CREDITS_EMPTY_VN1_SNP, 0x20, 0x20, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
QPI0_AD_CREDITS_EMPTY_VN1_NDR, 0x20, 0x40, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
QPI1_AD_CREDITS_EMPTY_VNA, 0x2E, 0x1, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
QPI1_AD_CREDITS_EMPTY_VN1_HOM, 0x2E, 0x10, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
QPI1_AD_CREDITS_EMPTY_VN1_SNP, 0x2E, 0x20, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
QPI1_AD_CREDITS_EMPTY_VN1_NDR, 0x2E, 0x40, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
QPI0_BL_CREDITS_EMPTY_VNA, 0x21, 0x1, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
QPI0_BL_CREDITS_EMPTY_VN1_HOM, 0x21, 0x10, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
QPI0_BL_CREDITS_EMPTY_VN1_SNP, 0x21, 0x20, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
QPI0_BL_CREDITS_EMPTY_VN1_NDR, 0x21, 0x40, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
QPI1_BL_CREDITS_EMPTY_VNA, 0x2F, 0x1, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
QPI1_BL_CREDITS_EMPTY_VN0_HOM, 0x2F, 0x2, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
QPI1_BL_CREDITS_EMPTY_VN0_SNP, 0x2F, 0x4, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
QPI1_BL_CREDITS_EMPTY_VN0_NDR, 0x2F, 0x8, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
QPI1_BL_CREDITS_EMPTY_VN1_HOM, 0x2F, 0x10, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
QPI1_BL_CREDITS_EMPTY_VN1_SNP, 0x2F, 0x20, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
QPI1_BL_CREDITS_EMPTY_VN1_NDR, 0x2F, 0x40, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
RING_AD_USED_CW_EVEN, 0x7, 0x1, RBOX
RING_AD_USED_CW_ODD, 0x7, 0x2, RBOX
RING_AD_USED_CW, 0x7, 0x3, RBOX
RING_AD_USED_CCW_EVEN, 0x7, 0x4, RBOX
RING_AD_USED_CCW_ODD, 0x7, 0x8, RBOX
RING_AD_USED_CCW, 0x7, 0xC, RBOX
RING_AK_USED_CW_EVEN, 0x8, 0x1, RBOX
RING_AK_USED_CW_ODD, 0x8, 0x2, RBOX
RING_AK_USED_CW, 0x8, 0x3, RBOX
RING_AK_USED_CCW_EVEN, 0x8, 0x4, RBOX
RING_AK_USED_CCW_ODD, 0x8, 0x8, RBOX
RING_AK_USED_CCW, 0x8, 0xC, RBOX
RING_BL_USED_CW_EVEN, 0x9, 0x1, RBOX
RING_BL_USED_CW_ODD, 0x9, 0x2, RBOX
RING_BL_USED_CW, 0x9, 0x3, RBOX
RING_BL_USED_CCW_EVEN, 0x9, 0x4, RBOX
RING_BL_USED_CCW_ODD, 0x9, 0x8, RBOX
RING_BL_USED_CCW, 0x9, 0xC, RBOX
RING_IV_USED_CW, 0xA, 0x3, RBOX
RING_IV_USED_CCW, 0xA, 0xC, RBOX
RING_IV_USED_ANY, 0xA, 0xF, RBOX
RING_SINK_STARVED_AK, 0xE, 0x2, RBOX
RXR_CYCLES_NE_HOM, 0x10, 0x1, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
RXR_CYCLES_NE_SNP, 0x10, 0x2, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
RXR_CYCLES_NE_NDR, 0x10, 0x4, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
RXR_CYCLES_NE_VN1_HOM, 0x14, 0x1, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
RXR_CYCLES_NE_VN1_SNP, 0x14, 0x2, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
RXR_CYCLES_NE_VN1_NDR, 0x14, 0x4, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
RXR_CYCLES_NE_VN1_DRS, 0x14, 0x8, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
RXR_CYCLES_NE_VN1_NCB, 0x14, 0x10, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
RXR_CYCLES_NE_VN1_NCS, 0x14, 0x20, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
RXR_INSERTS_HOM, 0x11, 0x1, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
RXR_INSERTS_SNP, 0x11, 0x2, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
RXR_INSERTS_NDR, 0x11, 0x4, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
RXR_INSERTS_DRS, 0x11, 0x8, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
RXR_INSERTS_NCB, 0x11, 0x10, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
RXR_INSERTS_NCS, 0x11, 0x20, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
RXR_INSERTS_VN1_HOM, 0x15, 0x1, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
RXR_INSERTS_VN1_SNP, 0x15, 0x2, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
RXR_INSERTS_VN1_NDR, 0x15, 0x4, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
RXR_INSERTS_VN1_DRS, 0x15, 0x8, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
RXR_INSERTS_VN1_NCB, 0x15, 0x10, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
RXR_INSERTS_VN1_NCS, 0x15, 0x20, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
RXR_OCCUPANCY_VN1_HOM, 0x13, 0x1, RBOX0C0|RBOX1C0
RXR_OCCUPANCY_VN1_SNP, 0x13, 0x2, RBOX0C0|RBOX1C0
RXR_OCCUPANCY_VN1_NDR, 0x13, 0x4, RBOX0C0|RBOX1C0
RXR_OCCUPANCY_VN1_DRS, 0x13, 0x8, RBOX0C0|RBOX1C0
RXR_OCCUPANCY_VN1_NCB, 0x13, 0x10, RBOX0C0|RBOX1C0
RXR_OCCUPANCY_VN1_NCS, 0x13, 0x20, RBOX0C0|RBOX1C0
TXR_CYCLES_FULL, 0x25, 0x0, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
TXR_CYCLES_NE, 0x23, 0x0, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
TXR_NACK_DN_AD, 0x26, 0x1, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
TXR_NACK_DN_BL, 0x26, 0x2, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
TXR_NACK_DN_AK, 0x26, 0x4, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
TXR_NACK_UP_AD, 0x26, 0x8, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
TXR_NACK_UP_BL, 0x26, 0x10, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
TXR_NACK_UP_AK, 0x26, 0x20, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
SBO0_CREDITS_ACQUIRED_AD, 0x28, 0x1, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
SBO0_CREDITS_ACQUIRED_BL, 0x28, 0x2, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
SBO1_CREDITS_ACQUIRED_AD, 0x29, 0x1, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
SBO1_CREDITS_ACQUIRED_BL, 0x29, 0x2, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
STALL_NO_SBO_CREDIT_SBO0_AD, 0x2C, 0x1, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
STALL_NO_SBO_CREDIT_SBO1_AD, 0x2C, 0x2, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
STALL_NO_SBO_CREDIT_SBO0_BL, 0x2C, 0x4, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
STALL_NO_SBO_CREDIT_SBO1_BL, 0x2C, 0x8, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
VN0_CREDITS_REJECT_HOM, 0x37, 0x1, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
VN0_CREDITS_REJECT_SNP, 0x37, 0x2, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
VN0_CREDITS_REJECT_NDR, 0x37, 0x4, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
VN0_CREDITS_REJECT_DRS, 0x37, 0x8, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
VN0_CREDITS_REJECT_NCB, 0x37, 0x10, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
VN0_CREDITS_REJECT_NCS, 0x37, 0x20, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
VN1_CREDITS_REJECT_HOM, 0x39, 0x1, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
VN1_CREDITS_REJECT_SNP, 0x39, 0x2, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
VN1_CREDITS_REJECT_NDR, 0x39, 0x4, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
VN1_CREDITS_REJECT_DRS, 0x39, 0x8, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
VN1_CREDITS_REJECT_NCB, 0x39, 0x10, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
VN1_CREDITS_REJECT_NCS, 0x39, 0x20, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
VNA_CREDITS_REJECT_HOM, 0x34, 0x1, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
VNA_CREDITS_REJECT_SNP, 0x34, 0x2, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
VNA_CREDITS_REJECT_NDR, 0x34, 0x4, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
VNA_CREDITS_REJECT_DRS, 0x34, 0x8, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
VNA_CREDITS_REJECT_NCB, 0x34, 0x10, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
VNA_CREDITS_REJECT_NCS, 0x34, 0x20, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
VN0_CREDITS_USED_HOM, 0x36, 0x1, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
VN0_CREDITS_USED_SNP, 0x36, 0x2, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
VN0_CREDITS_USED_NDR, 0x36, 0x4, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
VN0_CREDITS_USED_DRS, 0x36, 0x8, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
VN0_CREDITS_USED_NCB, 0x36, 0x10, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
VN0_CREDITS_USED_NCS, 0x36, 0x20, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
VN1_CREDITS_USED_HOM, 0x38, 0x1, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
VN1_CREDITS_USED_SNP, 0x38, 0x2, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
VN1_CREDITS_USED_NDR, 0x38, 0x4, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
VN1_CREDITS_USED_DRS, 0x38, 0x8, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
VN1_CREDITS_USED_NCB, 0x38, 0x10, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
VN1_CREDITS_USED_NCS, 0x38, 0x20, RBOX0C0|RBOX0C1|RBOX1C0|RBOX1C1
BOUNCE_CONTROL, 0xA, 0x0, SBOX
SBOX_CLOCKTICKS, 0x0, 0x0, SBOX
FAST_ASSERTED, 0x9, 0x0, SBOX
RING_AD_USED_ANY, 0x1B, 0xF, SBOX
RING_AD_USED_UP_EVEN, 0x1B, 0x1, SBOX
RING_AD_USED_UP_ODD, 0x1B, 0x2, SBOX
RING_AD_USED_UP, 0x1B, 0x3, SBOX
RING_AD_USED_DOWN_EVEN, 0x1B, 0x4, SBOX
RING_AD_USED_DOWN_ODD, 0x1B, 0x8, SBOX
RING_AD_USED_DOWN, 0x1B, 0xC, SBOX
RING_AK_USED_ANY, 0x1C, 0xF, SBOX
RING_AK_USED_UP_EVEN, 0x1C, 0x1, SBOX
RING_AK_USED_UP_ODD, 0x1C, 0x2, SBOX
RING_AK_USED_UP, 0x1C, 0x3, SBOX
RING_AK_USED_DOWN_EVEN, 0x1C, 0x4, SBOX
RING_AK_USED_DOWN_ODD, 0x1C, 0x8, SBOX
RING_AK_USED_DOWN, 0x1C, 0xC, SBOX
RING_BL_USED_ANY, 0x1D, 0xF, SBOX
RING_BL_USED_UP_EVEN, 0x1D, 0x1, SBOX
RING_BL_USED_UP_ODD, 0x1D, 0x2, SBOX
RING_BL_USED_UP, 0x1D, 0x3, SBOX
RING_BL_USED_DOWN_EVEN, 0x1D, 0x4, SBOX
RING_BL_USED_DOWN_ODD, 0x1D, 0x8, SBOX
RING_BL_USED_DOWN, 0x1D, 0xC, SBOX
RING_BOUNCES_AD_CACHE, 0x5, 0x1, SBOX
RING_BOUNCES_AK_CORE, 0x5, 0x2, SBOX
RING_BOUNCES_BL_CORE, 0x5, 0x4, SBOX
RING_BOUNCES_IV_CORE, 0x5, 0x8, SBOX
RING_IV_USED_ANY, 0x1E, 0xF, SBOX
RING_IV_USED_UP, 0x1E, 0x3, SBOX
RING_IV_USED_DOWN, 0x1E, 0xC, SBOX
RXR_BYPASS_AD_CRD, 0x12, 0x1, SBOX
RXR_BYPASS_AD_BNC, 0x12, 0x2, SBOX
RXR_BYPASS_BL_CRD, 0x12, 0x4, SBOX
RXR_BYPASS_BL_BNC, 0x12, 0x8, SBOX
RXR_BYPASS_AK, 0x12, 0x10, SBOX
RXR_BYPASS_IV, 0x12, 0x20, SBOX
RXR_INSERTS_AD_CRD, 0x12, 0x1, SBOX
RXR_INSERTS_AD_BNC, 0x12, 0x2, SBOX
RXR_INSERTS_BL_CRD, 0x12, 0x4, SBOX
RXR_INSERTS_BL_BNC, 0x12, 0x8, SBOX
RXR_INSERTS_AK, 0x12, 0x10, SBOX
RXR_INSERTS_IV, 0x12, 0x20, SBOX
RXR_OCCUPANCY_AD_CRD, 0x11, 0x1, SBOX
RXR_OCCUPANCY_AD_BNC, 0x11, 0x2, SBOX
RXR_OCCUPANCY_BL_CRD, 0x11, 0x4, SBOX
RXR_OCCUPANCY_BL_BNC, 0x11, 0x8, SBOX
RXR_OCCUPANCY_AK, 0x11, 0x10, SBOX
RXR_OCCUPANCY_IV, 0x11, 0x20, SBOX
TXR_ADS_USED_AD, 0x4, 0x1, SBOX
TXR_ADS_USED_AK, 0x4, 0x2, SBOX
TXR_ADS_USED_BL, 0x4, 0x4, SBOX
TXR_INSERTS_AD_CRD, 0x2, 0x1, SBOX
TXR_INSERTS_AD_BNC, 0x2, 0x2, SBOX
TXR_INSERTS_BL_CRD, 0x2, 0x4, SBOX
TXR_INSERTS_BL_BNC, 0x2, 0x8, SBOX
TXR_INSERTS_AK, 0x2, 0x10, SBOX
TXR_INSERTS_IV, 0x2, 0x20, SBOX
TXR_OCCUPANCY_AD_CRD, 0x1, 0x1, SBOX
TXR_OCCUPANCY_AD_BNC, 0x1, 0x2, SBOX
TXR_OCCUPANCY_BL_CRD, 0x1, 0x4, SBOX
TXR_OCCUPANCY_BL_BNC, 0x1, 0x8, SBOX
TXR_OCCUPANCY_AK, 0x1, 0x10, SBOX
TXR_OCCUPANCY_IV, 0x1, 0x20, SBOX
TXR_ORDERING_IV_SNOOPGO_UP, 0x7, 0x1, SBOX
TXR_ORDERING_IV_SNOOPGO_DN, 0x7, 0x2, SBOX
TXR_ORDERING_AK_U2C_UP_EVEN, 0x7, 0x4, SBOX
TXR_ORDERING_AK_U2C_UP_ODD, 0x7, 0x8, SBOX
TXR_ORDERING_AK_U2C_DN_EVEN, 0x7, 0x10, SBOX
TXR_ORDERING_AK_U2C_DN_ODD, 0x7, 0x20, SBOX
QBOX_CLOCKTICKS, 0x14, 0x0, QBOX
CTO_COUNT, 0x38, 0x0, QBOX, MATCH0|MATCH1|MATCH2|MATCH3|MASK0|MASK1|MASK2|MASK3
DIRECT2CORE_SUCCESS_RBT_HIT, 0x13, 0x1, QBOX
DIRECT2CORE_FAILURE_CREDITS, 0x13, 0x2, QBOX
DIRECT2CORE_FAILURE_RBT_HIT, 0x13, 0x4, QBOX
DIRECT2CORE_FAILURE_CREDITS_RBT, 0x13, 0x8, QBOX
DIRECT2CORE_FAILURE_MISS, 0x13, 0x10, QBOX
DIRECT2CORE_FAILURE_CREDITS_MISS, 0x13, 0x20, QBOX
DIRECT2CORE_FAILURE_RBT_MISS, 0x13, 0x40, QBOX
DIRECT2CORE_FAILURE_CREDITS_RBT_MISS, 0x13, 0x80, QBOX
L1_POWER_CYCLES, 0x12, 0x0, QBOX
RXL0P_POWER_CYCLES, 0x10, 0x0, QBOX
RXL0_POWER_CYCLES, 0xF, 0x0, QBOX
RXL_BYPASSED, 0x9, 0x0, QBOX
RXL_CREDITS_CONSUMED_VN0_DRS, 0x1E, 0x1, QBOX
RXL_CREDITS_CONSUMED_VN0_NCB, 0x1E, 0x2, QBOX
RXL_CREDITS_CONSUMED_VN0_NCS, 0x1E, 0x4, QBOX
RXL_CREDITS_CONSUMED_VN0_HOM, 0x1E, 0x8, QBOX
RXL_CREDITS_CONSUMED_VN0_SNP, 0x1E, 0x10, QBOX
RXL_CREDITS_CONSUMED_VN0_NDR, 0x1E, 0x20, QBOX
RXL_CREDITS_CONSUMED_VN1_DRS, 0x39, 0x1, QBOX
RXL_CREDITS_CONSUMED_VN1_NCB, 0x39, 0x2, QBOX
RXL_CREDITS_CONSUMED_VN1_NCS, 0x39, 0x4, QBOX
RXL_CREDITS_CONSUMED_VN1_HOM, 0x39, 0x8, QBOX
RXL_CREDITS_CONSUMED_VN1_SNP, 0x39, 0x10, QBOX
RXL_CREDITS_CONSUMED_VN1_NDR, 0x39, 0x20, QBOX
RXL_CREDITS_CONSUMED_VNA, 0x1D, 0x0, QBOX
RXL_CYCLES_NE, 0xA, 0x0, QBOX
RXL_FLITS_G0_IDLE, 0x1, 0x1, QBOX
RXL_FLITS_G0_DATA, 0x1, 0x2, QBOX
RXL_FLITS_G0_NON_DATA, 0x1, 0x4, QBOX
RXL_FLITS_G1_SNP, 0x2, 0x1, QBOX
RXL_FLITS_G1_HOM_REQ, 0x2, 0x2, QBOX
RXL_FLITS_G1_HOM_NONREQ, 0x2, 0x4, QBOX
RXL_FLITS_G1_HOM, 0x2, 0x6, QBOX
RXL_FLITS_G1_DRS_DATA, 0x2, 0x8, QBOX
RXL_FLITS_G1_DRS_NONDATA, 0x2, 0x10, QBOX
RXL_FLITS_G1_DRS, 0x2, 0x18, QBOX
RXL_FLITS_G2_NDR_AD, 0x3, 0x1, QBOX
RXL_FLITS_G2_NDR_AK, 0x3, 0x2, QBOX
RXL_FLITS_G2_NCB_DATA, 0x3, 0x4, QBOX
RXL_FLITS_G2_NCB_NONDATA, 0x3, 0x8, QBOX
RXL_FLITS_G2_NCB, 0x3, 0xC, QBOX
RXL_FLITS_G2_NCS, 0x3, 0x10, QBOX
RXL_INSERTS, 0x8, 0x0, QBOX
RXL_INSERTS_DRS_VN0, 0x9, 0x1, QBOX
RXL_INSERTS_DRS_VN1, 0x9, 0x2, QBOX
RXL_INSERTS_HOM_VN0, 0xC, 0x1, QBOX
RXL_INSERTS_HOM_VN1, 0xC, 0x2, QBOX
RXL_INSERTS_NCB_VN0, 0xA, 0x1, QBOX
RXL_INSERTS_NCB_VN1, 0xA, 0x2, QBOX
RXL_INSERTS_NCS_VN0, 0xB, 0x1, QBOX
RXL_INSERTS_NCS_VN1, 0xB, 0x2, QBOX
RXL_INSERTS_NDR_VN0, 0xE, 0x1, QBOX
RXL_INSERTS_NDR_VN1, 0xE, 0x2, QBOX
RXL_INSERTS_SNP_VN0, 0xD, 0x1, QBOX
RXL_INSERTS_SNP_VN1, 0xD, 0x2, QBOX
RXL_OCCUPANCY, 0xB, 0x0, QBOX
RXL_OCCUPANCY_DRS_VN0, 0x15, 0x1, QBOX
RXL_OCCUPANCY_DRS_VN1, 0x15, 0x2, QBOX
RXL_OCCUPANCY_HOM_VN0, 0x18, 0x1, QBOX
RXL_OCCUPANCY_HOM_VN1, 0x18, 0x2, QBOX
RXL_OCCUPANCY_NCB_VN0, 0x16, 0x1, QBOX
RXL_OCCUPANCY_NCB_VN1, 0x16, 0x2, QBOX
RXL_OCCUPANCY_NCS_VN0, 0x17, 0x1, QBOX
RXL_OCCUPANCY_NCS_VN1, 0x17, 0x2, QBOX
RXL_OCCUPANCY_NDR_VN0, 0x1A, 0x1, QBOX
RXL_OCCUPANCY_NDR_VN1, 0x1A, 0x2, QBOX
RXL_OCCUPANCY_SNP_VN0, 0x19, 0x1, QBOX
RXL_OCCUPANCY_SNP_VN1, 0x19, 0x2, QBOX
TXL0P_POWER_CYCLES, 0xD, 0x0, QBOX
TXL0_POWER_CYCLES, 0xC, 0x0, QBOX
TXL_BYPASSED, 0x5, 0x0, QBOX
TXL_CYCLES_NE, 0x6, 0x0, QBOX
TXL_FLITS_G0_IDLE, 0x0, 0x1, QBOX
TXL_FLITS_G0_DATA, 0x0, 0x2, QBOX
TXL_FLITS_G0_NON_DATA, 0x0, 0x4, QBOX
TXL_FLITS_G1_SNP, 0x0, 0x1, QBOX
TXL_FLITS_G1_HOM_REQ, 0x0, 0x2, QBOX
TXL_FLITS_G1_HOM_NONREQ, 0x0, 0x4, QBOX
TXL_FLITS_G1_HOM, 0x0, 0x6, QBOX
TXL_FLITS_G1_DRS_DATA, 0x0, 0x8, QBOX
TXL_FLITS_G1_DRS_NONDATA, 0x0, 0x10, QBOX
TXL_FLITS_G1_DRS, 0x0, 0x18, QBOX
TXL_FLITS_G2_NDR_AD, 0x1, 0x1, QBOX
TXL_FLITS_G2_NDR_AK, 0x1, 0x2, QBOX
TXL_FLITS_G2_NCB_DATA, 0x1, 0x4, QBOX
TXL_FLITS_G2_NCB_NONDATA, 0x1, 0x8, QBOX
TXL_FLITS_G2_NCB, 0x1, 0xC, QBOX
TXL_FLITS_G2_NCS, 0x1, 0x10, QBOX
TXL_INSERTS, 0x4, 0x0, QBOX
TXL_OCCUPANCY, 0x7, 0x0, QBOX
TXR_AD_HOM_CREDIT_ACQUIRED_VN0, 0x26, 0x1, QBOX
TXR_AD_HOM_CREDIT_ACQUIRED_VN1, 0x26, 0x2, QBOX
TXR_AD_HOM_CREDIT_OCCUPANCY_VN0, 0x22, 0x1, QBOX
TXR_AD_HOM_CREDIT_OCCUPANCY_VN1, 0x22, 0x2, QBOX
TXR_AD_NDR_CREDIT_ACQUIRED_VN0, 0x28, 0x1, QBOX
TXR_AD_NDR_CREDIT_ACQUIRED_VN1, 0x28, 0x2, QBOX
TXR_AD_NDR_CREDIT_OCCUPANCY_VN0, 0x24, 0x1, QBOX
TXR_AD_NDR_CREDIT_OCCUPANCY_VN1, 0x24, 0x2, QBOX
TXR_AD_SNP_CREDIT_ACQUIRED_VN0, 0x27, 0x1, QBOX
TXR_AD_SNP_CREDIT_ACQUIRED_VN1, 0x27, 0x2, QBOX
TXR_AD_SNP_CREDIT_OCCUPANCY_VN0, 0x23, 0x1, QBOX
TXR_AD_SNP_CREDIT_OCCUPANCY_VN1, 0x23, 0x2, QBOX
TXR_AK_NDR_CREDIT_ACQUIRED, 0x29, 0x0, QBOX
TXR_AK_NDR_CREDIT_OCCUPANCY, 0x25, 0x0, QBOX
TXR_BL_DRS_CREDIT_ACQUIRED_VN0, 0x2A, 0x1, QBOX
TXR_BL_DRS_CREDIT_ACQUIRED_VN1, 0x2A, 0x2, QBOX
TXR_BL_DRS_CREDIT_ACQUIRED_VN_SHR, 0x2A, 0x4, QBOX
TXR_BL_DRS_CREDIT_OCCUPANCY_VN0, 0x1F, 0x1, QBOX
TXR_BL_DRS_CREDIT_OCCUPANCY_VN1, 0x1F, 0x2, QBOX
TXR_BL_DRS_CREDIT_OCCUPANCY_VN_SHR, 0x1F, 0x4, QBOX
TXR_BL_NCB_CREDIT_ACQUIRED_VN0, 0x2B, 0x1, QBOX
TXR_BL_NCB_CREDIT_ACQUIRED_VN1, 0x2B, 0x2, QBOX
TXR_BL_NCB_CREDIT_OCCUPANCY_VN0, 0x20, 0x1, QBOX
TXR_BL_NCB_CREDIT_OCCUPANCY_VN1, 0x20, 0x2, QBOX
TXR_BL_NCS_CREDIT_ACQUIRED_VN0, 0x2C, 0x1, QBOX
TXR_BL_NCS_CREDIT_ACQUIRED_VN1, 0x2C, 0x2, QBOX
TXR_BL_NCS_CREDIT_OCCUPANCY_VN0, 0x21, 0x1, QBOX
TXR_BL_NCS_CREDIT_OCCUPANCY_VN1, 0x21, 0x2, QBOX
VNA_CREDIT_RETURNS, 0x1C, 0x0, QBOX
VNA_CREDIT_RETURN_OCCUPANCY, 0x1B, 0x0, QBOX
QPI_RATE, 0x0, 0x0, QBOX0FIX0|QBOX1FIX0|QBOX2FIX0
QPI_RX_IDLE, 0x1, 0x0, QBOX0FIX1|QBOX1FIX1|QBOX2FIX1
QPI_RX_LLR, 0x2, 0x0, QBOX0FIX2|QBOX1FIX2|QBOX2FIX2
In [3]:
!likwid-perfctr -a
 Group name	Description
--------------------------------------------------------------------------------
  FLOPS_AVX	Packed AVX MFLOP/s
  TLB_INSTR	L1 Instruction TLB miss rate/ratio
       NUMA	Local and remote memory accesses
     ENERGY	Power and Energy consumption
   TLB_DATA	L2 data TLB miss rate/ratio
      CLOCK	Power and Energy consumption
 PORT_USAGE	Execution port utilization
CYCLE_ACTIVITY	Cycle Activities
       UOPS	UOPs execution info
        QPI	QPI Link Layer data
         L2	L2 cache bandwidth in MBytes/s
     CACHES	Cache bandwidth in MBytes/s
     BRANCH	Branch prediction miss rate/ratio
       DATA	Load to store ratio
   RECOVERY	Recovery duration
  UOPS_EXEC	UOPs execution
        MEM	Main memory bandwidth in MBytes/s
 UOPS_ISSUE	UOPs issueing
     ICACHE	Instruction cache miss rate/ratio
    L3CACHE	L3 cache miss rate/ratio
    L2CACHE	L2 cache miss rate/ratio
       SBOX	Ring Transfer bandwidth
         HA	Main memory bandwidth in MBytes/s seen from Home agent
FALSE_SHARE	False sharing
UOPS_RETIRE	UOPs retirement
         L3	L3 cache bandwidth in MBytes/s
       CBOX	CBOX related data and metrics
In [28]:
!likwid-perfctr -H -g MEM
Group MEM:
Formulas:
Memory read bandwidth [MBytes/s] = 1.0E-06*(SUM(MBOXxC0))*64.0/runtime
Memory read data volume [GBytes] = 1.0E-09*(SUM(MBOXxC0))*64.0
Memory write bandwidth [MBytes/s] = 1.0E-06*(SUM(MBOXxC1))*64.0/runtime
Memory write data volume [GBytes] = 1.0E-09*(SUM(MBOXxC1))*64.0
Memory bandwidth [MBytes/s] = 1.0E-06*(SUM(MBOXxC0)+SUM(MBOXxC1))*64.0/runtime
Memory data volume [GBytes] = 1.0E-09*(SUM(MBOXxC0)+SUM(MBOXxC1))*64.0
-
Profiling group to measure memory bandwidth drawn by all cores of a socket.
Since this group is based on Uncore events it is only possible to measure on a
per socket base. Some of the counters may not be available on your system.
Also outputs total data volume transferred from main memory.
The same metrics are provided by the HA group.

In [15]:
%%writefile tmp/perfctr.py

import numpy as np
import likwid

likwid.init_thread()
likwid.init_openmp_threads()

n = 2048

with likwid.Region("generation"):
    A = np.random.randn(n, n)
    b = np.random.randn(n)

with likwid.Region("matmul"):
    A @ A
Overwriting tmp/perfctr.py

Also add -m option below.

  • Advantages?
  • Disadvantages?

Make sure the MSR access daemon is SUID root:

chmod u+s /usr/sbin/likwid-accessD
In [18]:
!likwid-perfctr -C S0:0-7@S1:0-7 -M 1 -g MEM python3 ./tmp/perfctr.py
--------------------------------------------------------------------------------
CPU name:	Intel(R) Xeon(R) CPU E5-2650 v4 @ 2.20GHz
CPU type:	Intel Xeon Broadwell EN/EP/EX processor
CPU clock:	2.19 GHz
--------------------------------------------------------------------------------
Running without Marker API. Activate Marker API with -m on commandline.
--------------------------------------------------------------------------------
Group 1: MEM
+-----------------------+---------+------------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+----------+-----------+
|         Event         | Counter |   Core 0   |   Core 1  |   Core 2  |   Core 3  |   Core 4  |   Core 5  |   Core 6  |   Core 7  |  Core 12  |  Core 13  |  Core 14  |  Core 15  |  Core 16  |  Core 17  |  Core 18 |  Core 19  |
+-----------------------+---------+------------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+----------+-----------+
|   INSTR_RETIRED_ANY   |  FIXC0  | 1949520384 | 356458518 | 364873900 | 362027043 | 352323878 | 340961083 | 339418061 | 340180266 | 329162139 | 438126876 | 323908544 | 320824436 | 315188456 | 309798621 | 25306192 | 339338862 |
| CPU_CLK_UNHALTED_CORE |  FIXC1  | 1116681108 | 256556129 | 272782533 | 268002653 | 250929834 | 233567786 | 231861324 | 227811152 | 216251858 | 294065131 | 206608401 | 200982634 | 191193868 | 182247701 | 40194541 | 230682461 |
|  CPU_CLK_UNHALTED_REF |  FIXC2  | 1133365728 | 336271012 | 303399030 | 298917234 | 291128508 | 278965060 | 277807860 | 284598006 | 275326590 | 392295904 | 271997726 | 270141696 | 264090640 | 259688220 | 54866878 | 326025546 |
|      CAS_COUNT_RD     | MBOX0C0 |      -     |     -     |     -     |     -     |     -     |     -     |     -     |     -     |     -     |     -     |     -     |     -     |     -     |     -     |     -    |     -     |
|      CAS_COUNT_WR     | MBOX0C1 |      -     |     -     |     -     |     -     |     -     |     -     |     -     |     -     |     -     |     -     |     -     |     -     |     -     |     -     |     -    |     -     |
|      CAS_COUNT_RD     | MBOX1C0 |      -     |     -     |     -     |     -     |     -     |     -     |     -     |     -     |     -     |     -     |     -     |     -     |     -     |     -     |     -    |     -     |
|      CAS_COUNT_WR     | MBOX1C1 |      -     |     -     |     -     |     -     |     -     |     -     |     -     |     -     |     -     |     -     |     -     |     -     |     -     |     -     |     -    |     -     |
|      CAS_COUNT_RD     | MBOX2C0 |    1841226 |         0 |         0 |         0 |         0 |         0 |         0 |         0 |    297400 |         0 |         0 |         0 |         0 |         0 |        0 |         0 |
|      CAS_COUNT_WR     | MBOX2C1 |    1764762 |         0 |         0 |         0 |         0 |         0 |         0 |         0 |    169316 |         0 |         0 |         0 |         0 |         0 |        0 |         0 |
|      CAS_COUNT_RD     | MBOX3C0 |    1719502 |         0 |         0 |         0 |         0 |         0 |         0 |         0 |    395703 |         0 |         0 |         0 |         0 |         0 |        0 |         0 |
|      CAS_COUNT_WR     | MBOX3C1 |    1643243 |         0 |         0 |         0 |         0 |         0 |         0 |         0 |    268513 |         0 |         0 |         0 |         0 |         0 |        0 |         0 |
|      CAS_COUNT_RD     | MBOX4C0 |      -     |     -     |     -     |     -     |     -     |     -     |     -     |     -     |     -     |     -     |     -     |     -     |     -     |     -     |     -    |     -     |
|      CAS_COUNT_WR     | MBOX4C1 |      -     |     -     |     -     |     -     |     -     |     -     |     -     |     -     |     -     |     -     |     -     |     -     |     -     |     -     |     -    |     -     |
|      CAS_COUNT_RD     | MBOX5C0 |      -     |     -     |     -     |     -     |     -     |     -     |     -     |     -     |     -     |     -     |     -     |     -     |     -     |     -     |     -    |     -     |
|      CAS_COUNT_WR     | MBOX5C1 |      -     |     -     |     -     |     -     |     -     |     -     |     -     |     -     |     -     |     -     |     -     |     -     |     -     |     -     |     -    |     -     |
|      CAS_COUNT_RD     | MBOX6C0 |    1837196 |         0 |         0 |         0 |         0 |         0 |         0 |         0 |    293754 |         0 |         0 |         0 |         0 |         0 |        0 |         0 |
|      CAS_COUNT_WR     | MBOX6C1 |    1762917 |         0 |         0 |         0 |         0 |         0 |         0 |         0 |    167864 |         0 |         0 |         0 |         0 |         0 |        0 |         0 |
|      CAS_COUNT_RD     | MBOX7C0 |    1715048 |         0 |         0 |         0 |         0 |         0 |         0 |         0 |    392383 |         0 |         0 |         0 |         0 |         0 |        0 |         0 |
|      CAS_COUNT_WR     | MBOX7C1 |    1641179 |         0 |         0 |         0 |         0 |         0 |         0 |         0 |    266912 |         0 |         0 |         0 |         0 |         0 |        0 |         0 |
+-----------------------+---------+------------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+----------+-----------+

+----------------------------+---------+------------+----------+------------+--------------+
|            Event           | Counter |     Sum    |    Min   |     Max    |      Avg     |
+----------------------------+---------+------------+----------+------------+--------------+
|   INSTR_RETIRED_ANY STAT   |  FIXC0  | 6807417259 | 25306192 | 1949520384 | 4.254636e+08 |
| CPU_CLK_UNHALTED_CORE STAT |  FIXC1  | 4420419114 | 40194541 | 1116681108 | 2.762762e+08 |
|  CPU_CLK_UNHALTED_REF STAT |  FIXC2  | 5318885638 | 54866878 | 1133365728 | 3.324304e+08 |
|      CAS_COUNT_RD STAT     | MBOX0C0 |          0 |        0 |          0 |            0 |
|      CAS_COUNT_WR STAT     | MBOX0C1 |          0 |        0 |          0 |            0 |
|      CAS_COUNT_RD STAT     | MBOX1C0 |          0 |        0 |          0 |            0 |
|      CAS_COUNT_WR STAT     | MBOX1C1 |          0 |        0 |          0 |            0 |
|      CAS_COUNT_RD STAT     | MBOX2C0 |    2138626 |        0 |    1841226 |  133664.1250 |
|      CAS_COUNT_WR STAT     | MBOX2C1 |    1934078 |        0 |    1764762 |  120879.8750 |
|      CAS_COUNT_RD STAT     | MBOX3C0 |    2115205 |        0 |    1719502 |  132200.3125 |
|      CAS_COUNT_WR STAT     | MBOX3C1 |    1911756 |        0 |    1643243 |  119484.7500 |
|      CAS_COUNT_RD STAT     | MBOX4C0 |          0 |        0 |          0 |            0 |
|      CAS_COUNT_WR STAT     | MBOX4C1 |          0 |        0 |          0 |            0 |
|      CAS_COUNT_RD STAT     | MBOX5C0 |          0 |        0 |          0 |            0 |
|      CAS_COUNT_WR STAT     | MBOX5C1 |          0 |        0 |          0 |            0 |
|      CAS_COUNT_RD STAT     | MBOX6C0 |    2130950 |        0 |    1837196 |  133184.3750 |
|      CAS_COUNT_WR STAT     | MBOX6C1 |    1930781 |        0 |    1762917 |  120673.8125 |
|      CAS_COUNT_RD STAT     | MBOX7C0 |    2107431 |        0 |    1715048 |  131714.4375 |
|      CAS_COUNT_WR STAT     | MBOX7C1 |    1908091 |        0 |    1641179 |  119255.6875 |
+----------------------------+---------+------------+----------+------------+--------------+

+-----------------------------------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+
|               Metric              |   Core 0  |   Core 1  |   Core 2  |   Core 3  |   Core 4  |   Core 5  |   Core 6  |   Core 7  |  Core 12  |  Core 13  |  Core 14  |  Core 15  |  Core 16  |  Core 17  |  Core 18  |  Core 19  |
+-----------------------------------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+
|        Runtime (RDTSC) [s]        |    1.0019 |    1.0019 |    1.0019 |    1.0019 |    1.0019 |    1.0019 |    1.0019 |    1.0019 |    1.0019 |    1.0019 |    1.0019 |    1.0019 |    1.0019 |    1.0019 |    1.0019 |    1.0019 |
|        Runtime unhalted [s]       |    0.5088 |    0.1169 |    0.1243 |    0.1221 |    0.1143 |    0.1064 |    0.1056 |    0.1038 |    0.0985 |    0.1340 |    0.0941 |    0.0916 |    0.0871 |    0.0830 |    0.0183 |    0.1051 |
|            Clock [MHz]            | 2162.4963 | 1674.5158 | 1973.3251 | 1967.8157 | 1891.7504 | 1837.6356 | 1831.8084 | 1756.8691 | 1723.8837 | 1645.2278 | 1667.1665 | 1632.9135 | 1588.9756 | 1540.3027 | 1607.8780 | 1552.9562 |
|                CPI                |    0.5728 |    0.7197 |    0.7476 |    0.7403 |    0.7122 |    0.6850 |    0.6831 |    0.6697 |    0.6570 |    0.6712 |    0.6379 |    0.6265 |    0.6066 |    0.5883 |    1.5883 |    0.6798 |
|  Memory read bandwidth [MBytes/s] |  454.3715 |         0 |         0 |         0 |         0 |         0 |         0 |         0 |   88.1049 |         0 |         0 |         0 |         0 |         0 |         0 |         0 |
|  Memory read data volume [GBytes] |    0.4552 |         0 |         0 |         0 |         0 |         0 |         0 |         0 |    0.0883 |         0 |         0 |         0 |         0 |         0 |         0 |         0 |
| Memory write bandwidth [MBytes/s] |  435.1521 |         0 |         0 |         0 |         0 |         0 |         0 |         0 |   55.7414 |         0 |         0 |         0 |         0 |         0 |         0 |         0 |
| Memory write data volume [GBytes] |    0.4360 |         0 |         0 |         0 |         0 |         0 |         0 |         0 |    0.0558 |         0 |         0 |         0 |         0 |         0 |         0 |         0 |
|    Memory bandwidth [MBytes/s]    |  889.5237 |         0 |         0 |         0 |         0 |         0 |         0 |         0 |  143.8462 |         0 |         0 |         0 |         0 |         0 |         0 |         0 |
|    Memory data volume [GBytes]    |    0.8912 |         0 |         0 |         0 |         0 |         0 |         0 |         0 |    0.1441 |         0 |         0 |         0 |         0 |         0 |         0 |         0 |
+-----------------------------------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+-----------+

+----------------------------------------+------------+-----------+-----------+-----------+
|                 Metric                 |     Sum    |    Min    |    Max    |    Avg    |
+----------------------------------------+------------+-----------+-----------+-----------+
|        Runtime (RDTSC) [s] STAT        |    16.0304 |    1.0019 |    1.0019 |    1.0019 |
|        Runtime unhalted [s] STAT       |     2.0139 |    0.0183 |    0.5088 |    0.1259 |
|            Clock [MHz] STAT            | 28055.5204 | 1540.3027 | 2162.4963 | 1753.4700 |
|                CPI STAT                |    11.5860 |    0.5728 |    1.5883 |    0.7241 |
|  Memory read bandwidth [MBytes/s] STAT |   542.4764 |         0 |  454.3715 |   33.9048 |
|  Memory read data volume [GBytes] STAT |     0.5435 |         0 |    0.4552 |    0.0340 |
| Memory write bandwidth [MBytes/s] STAT |   490.8935 |         0 |  435.1521 |   30.6808 |
| Memory write data volume [GBytes] STAT |     0.4918 |         0 |    0.4360 |    0.0307 |
|    Memory bandwidth [MBytes/s] STAT    |  1033.3699 |         0 |  889.5237 |   64.5856 |
|    Memory data volume [GBytes] STAT    |     1.0353 |         0 |    0.8912 |    0.0647 |
+----------------------------------------+------------+-----------+-----------+-----------+

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